/*
 * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     MAX78000.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     28. September 2022
 * @note     Generated by SVDConv V3.3.42 on Wednesday, 28.09.2022 12:49:04
 *           from File 'max78000.svd',
 *           last modified on Wednesday, 28.09.2022 04:47:04
 */



/** @addtogroup Maxim-Integrated
  * @{
  */


/** @addtogroup MAX78000
  * @{
  */


#ifndef MAX78000_H
#define MAX78000_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ==========================================  MAX78000 Specific Interrupt Numbers  ========================================== */
    PF_IRQn = 0,            /* 0x10  0x0040  16: Power Fail */
    WDT0_IRQn,              /* 0x11  0x0044  17: Watchdog 0 */
    RSV02_IRQn,             /* 0x12  0x0048  18: Reserved */
    RTC_IRQn,               /* 0x13  0x004C  19: RTC */
    TRNG_IRQn,              /* 0x14  0x0050  20: True Random Number Generator */
    TMR0_IRQn,              /* 0x15  0x0054  21: Timer 0 */
    TMR1_IRQn,              /* 0x16  0x0058  22: Timer 1 */
    TMR2_IRQn,              /* 0x17  0x005C  23: Timer 2 */
    TMR3_IRQn,              /* 0x18  0x0060  24: Timer 3 */
    TMR4_IRQn,              /* 0x19  0x0064  25: Timer 4 (LP) */
    TMR5_IRQn,              /* 0x1A  0x0068  26: Timer 5 (LP) */
    RSV11_IRQn,             /* 0x1B  0x006C  27: Reserved */
    RSV12_IRQn,             /* 0x1C  0x0070  28: Reserved */
    I2C0_IRQn,              /* 0x1D  0x0074  29: I2C0 */
    UART0_IRQn,             /* 0x1E  0x0078  30: UART 0 */
    UART1_IRQn,             /* 0x1F  0x007C  31: UART 1 */
    SPI1_IRQn,              /* 0x20  0x0080  32: SPI1 */
    RSV17_IRQn,             /* 0x21  0x0084  33: Reserved */
    RSV18_IRQn,             /* 0x22  0x0088  34: Reserved */
    RSV19_IRQn,             /* 0x23  0x008C  35: Reserved */
    ADC_IRQn,               /* 0x24  0x0090  36: ADC */
    RSV21_IRQn,             /* 0x25  0x0094  37: Reserved */
    RSV22_IRQn,             /* 0x26  0x0098  38: Reserved */
    FLC0_IRQn,              /* 0x27  0x009C  39: Flash Controller */
    GPIO0_IRQn,             /* 0x28  0x00A0  40: GPIO0 */
    GPIO1_IRQn,             /* 0x29  0x00A4  41: GPIO1 */
    GPIO2_IRQn,             /* 0x2A  0x00A8  42: GPIO2 (LP) */
    RSV27_IRQn,             /* 0x2B  0x00AC  43: Reserved */
    DMA0_IRQn,              /* 0x2C  0x00B0  44: DMA0 */
    DMA1_IRQn,              /* 0x2D  0x00B4  45: DMA1 */
    DMA2_IRQn,              /* 0x2E  0x00B8  46: DMA2 */
    DMA3_IRQn,              /* 0x2F  0x00BC  47: DMA3 */
    RSV32_IRQn,             /* 0x30  0x00C0  48: Reserved */
    RSV33_IRQn,             /* 0x31  0x00C4  49: Reserved */
    UART2_IRQn,             /* 0x32  0x00C8  50: UART 2 */
    RSV35_IRQn,             /* 0x33  0x00CC  51: Reserved */
    I2C1_IRQn,              /* 0x34  0x00D0  52: I2C1 */
    RSV37_IRQn,             /* 0x35  0x00D4  53: Reserved */
    RSV38_IRQn,             /* 0x36  0x00D8  54: Reserved */
    RSV39_IRQn,             /* 0x37  0x00DC  55: BTLE TX Done */
    RSV40_IRQn,             /* 0x38  0x00E0  56: BTLE RX Received */
    RSV41_IRQn,             /* 0x39  0x00E4  57: BTLE RX Energy Detected */
    RSV42_IRQn,             /* 0x3A  0x00E8  58: BTLE SFD Detected */
    RSV43_IRQn,             /* 0x3B  0x00EC  59: BTLE SFD Timeout*/
    RSV44_IRQn,             /* 0x3C  0x00F0  60: BTLE Timestamp*/
    RSV45_IRQn,             /* 0x3D  0x00F4  61: BTLE CFO Done */
    RSV46_IRQn,             /* 0x3E  0x00F8  62: BTLE Signal Detected */
    RSV47_IRQn,             /* 0x3F  0x00FC  63: BTLE AGC Event */
    RSV48_IRQn,             /* 0x40  0x0100  64: BTLE RFFE SPIM Done */
    RSV49_IRQn,             /* 0x41  0x0104  65: BTLE TX AES Done */
    RSV50_IRQn,             /* 0x42  0x0108  66: BTLE RX AES Done */
    RSV51_IRQn,             /* 0x43  0x010C  67: BTLE Invalid APB Address*/
    RSV52_IRQn,             /* 0x44  0x0110  68: BTLE IQ Data Valid */
    WUT_IRQn,               /* 0x45  0x0114  69: Wakeup Timer */
    GPIOWAKE_IRQn,          /* 0x46  0x0118  70: GPIO and AIN Wakeup */
    RSV55_IRQn,             /* 0x47  0x011C  71: Reserved */
    SPI0_IRQn,              /* 0x48  0x0120  72: SPI0 */
    WDT1_IRQn,              /* 0x49  0x0124  73: LP Watchdog */
    RSV58_IRQn,             /* 0x4A  0x0128  74: Reserved */
    PT_IRQn,                /* 0x4B  0x012C  75: Pulse Train */
    RSV60_IRQn,             /* 0x4C  0x0130  76: Reserved */
    RSV61_IRQn,             /* 0x4D  0x0134  77: Reserved */
    I2C2_IRQn,              /* 0x4E  0x0138  78: I2C2 */
    RISCV_IRQn,             /* 0x4F  0x013C  79: RISC-V */
    RSV64_IRQn,             /* 0x50  0x0140  80: Reserved */
    RSV65_IRQn,             /* 0x51  0x0144  81: Reserved */
    RSV66_IRQn,             /* 0x52  0x0148  82: Reserved */
    OWM_IRQn,               /* 0x53  0x014C  83: One Wire Master */
    RSV68_IRQn,             /* 0x54  0x0150  84: Reserved */
    RSV69_IRQn,             /* 0x55  0x0154  85: Reserved */
    RSV70_IRQn,             /* 0x56  0x0158  86: Reserved */
    RSV71_IRQn,             /* 0x57  0x015C  87: Reserved */
    RSV72_IRQn,             /* 0x58  0x0160  88: Reserved */
    RSV73_IRQn,             /* 0x59  0x0164  89: Reserved */
    RSV74_IRQn,             /* 0x5A  0x0168  90: Reserved */
    RSV75_IRQn,             /* 0x5B  0x016C  91: Reserved */
    RSV76_IRQn,             /* 0x5C  0x0170  92: Reserved */
    RSV77_IRQn,             /* 0x5D  0x0174  93: Reserved */
    RSV78_IRQn,             /* 0x5E  0x0178  94: Reserved */
    RSV79_IRQn,             /* 0x5F  0x017C  95: Reserved */
    RSV80_IRQn,             /* 0x60  0x0180  96: Reserved */
    RSV81_IRQn,             /* 0x61  0x0184  97: Reserved */
    ECC_IRQn,               /* 0x62  0x0188  98: ECC */
    DVS_IRQn,               /* 0x63  0x018C  99: DVS */
    SIMO_IRQn,              /* 0x64  0x0190 100: SIMO */
    RSV85_IRQn,             /* 0x65  0x0194 101: Reserved */
    RSV86_IRQn,             /* 0x66  0x0198 102: Reserved */
    RSV87_IRQn,             /* 0x67  0x019C 103: Reserved */
    UART3_IRQn,             /* 0x68  0x01A0 104: UART 3 (LP) */
    RSV89_IRQn,             /* 0x69  0x01A4 105: Reserved */
    RSV90_IRQn,             /* 0x6A  0x01A8 106: Reserved */
    PCIF_IRQn,              /* 0x6B  0x01AC 107: PCIF (Camera) */
    RSV92_IRQn,             /* 0x6C  0x01B0 108: Reserved */
    RSV93_IRQn,             /* 0x6D  0x01B4 109: Reserved */
    RSV94_IRQn,             /* 0x6E  0x01B8 110: Reserved */
    RSV95_IRQn,             /* 0x6F  0x01BC 111: Reserved */
    RSV96_IRQn,             /* 0x70  0x01C0 112: Reserved */
    AES_IRQn,               /* 0x71  0x01C4 113: AES */
    RSV98_IRQn,             /* 0x72  0x01C8 114: Reserved */
    I2S_IRQn,               /* 0x73  0x01CC 115: I2S */
    CNN_FIFO_IRQn,          /* 0x74  0x01D0 116: CNN FIFO */
    CNN_IRQn,               /* 0x75  0x01D4 117: CNN */
    RSV102_IRQn,            /* 0x76  0x01D8 118: Reserved */
    LPCMP_IRQn,             /* 0x77  0x01Dc 119: LP Comparator */
} IRQn_Type;


/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                 0x0201U       /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  1        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
#include "system_MAX78000.h"                    /*!< MAX78000 System                                                           */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                              Device Specific Cluster Section                              ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_clusters
  * @{
  */


/**
  * @brief dma_ch [CH] (DMA Channel registers.)
  */
typedef struct {
  __IM  uint32_t  RESERVED[64];
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000100) DMA Channel Control Register.                              */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000104) DMA Channel Status Register.                               */
  __IOM uint32_t  SRC;                          /*!< (@ 0x00000108) Source Device Address. If SRCINC=1, the counter
                                                                    bits are incremented by 1,2, or 4, depending
                                                                    on the data width of each AHB cycle. For
                                                                    peripheral transfers, some or all of the
                                                                    actual address bits are fixed. If SRCINC=0,
                                                                    this register remains constant. In the case
                                                                    where a count-to-zero condition occurs while
                                                                    RLDEN=1, the register is reloaded with the
                                                                    contents of DMA_SRC_RLD.                                   */
  __IOM uint32_t  DST;                          /*!< (@ 0x0000010C) Destination Device Address. For peripheral transfers,
                                                                    some or all of the actual address bits are
                                                                    fixed. If DSTINC=1, this register is incremented
                                                                    on every AHB write out of the DMA FIFO.
                                                                    They are incremented by 1, 2, or 4, depending
                                                                    on the data width of each AHB cycle. In
                                                                    the case where a count-to-zero condition
                                                                    occurs while RLDEN=1, the register is reloaded
                                                                    with DMA_DST_RLD.                                          */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000110) DMA Counter. The user loads this register with
                                                                    the number of bytes to transfer. This counter
                                                                    decreases on every AHB cycle into the DMA
                                                                    FIFO. The decrement will be 1, 2, or 4 depending
                                                                    on the data width of each AHB cycle. When
                                                                    the counter reaches 0, a count-to-zero condition
                                                                    is triggered.                                              */
  __IOM uint32_t  SRCRLD;                       /*!< (@ 0x00000114) Source Address Reload Value. The value of this
                                                                    register is loaded into DMA0_SRC upon a
                                                                    count-to-zero condition.                                   */
  __IOM uint32_t  DSTRLD;                       /*!< (@ 0x00000118) Destination Address Reload Value. The value of
                                                                    this register is loaded into DMA0_DST upon
                                                                    a count-to-zero condition.                                 */
  __IOM uint32_t  CNTRLD;                       /*!< (@ 0x0000011C) DMA Channel Count Reload Register.                         */
} dma_ch_Type;                                  /*!< Size = 288 (0x120)                                                        */


/** @} */ /* End of group Device_Peripheral_clusters */


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief 10-bit Analog to Digital Converter (ADC)
  */

typedef struct {                                /*!< (@ 0x40034000) ADC Structure                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) ADC Control                                                */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000004) ADC Status                                                 */
  __IOM uint32_t  DATA;                         /*!< (@ 0x00000008) ADC Output Data                                            */
  __IOM uint32_t  INTR;                         /*!< (@ 0x0000000C) ADC Interrupt Control Register                             */
  __IOM uint32_t  LIMIT[4];                     /*!< (@ 0x00000010) ADC Limit                                                  */
} ADC_Type;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                            AES                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief AES Keys. (AES)
  */

typedef struct {                                /*!< (@ 0x40074000) AES Structure                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) AES Control Register                                       */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000004) AES Status Register                                        */
  __IOM uint32_t  INTFL;                        /*!< (@ 0x00000008) AES Interrupt Flag Register                                */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x0000000C) AES Interrupt Enable Register                              */
  __IOM uint32_t  FIFO;                         /*!< (@ 0x00000010) AES Data Register                                          */
} AES_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                          AES_KEY                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief AES Key Registers. (AES_KEY)
  */

typedef struct {                                /*!< (@ 0x40078000) AES_KEY Structure                                          */
  __IOM uint32_t  AES_KEY0;                     /*!< (@ 0x00000000) AES Key 0.                                                 */
  __IOM uint32_t  AES_KEY1;                     /*!< (@ 0x00000004) AES Key 1.                                                 */
  __IOM uint32_t  AES_KEY2;                     /*!< (@ 0x00000008) AES Key 2.                                                 */
  __IOM uint32_t  AES_KEY3;                     /*!< (@ 0x0000000C) AES Key 3.                                                 */
  __IOM uint32_t  AES_KEY4;                     /*!< (@ 0x00000010) AES Key 4.                                                 */
  __IOM uint32_t  AES_KEY5;                     /*!< (@ 0x00000014) AES Key 5.                                                 */
  __IOM uint32_t  AES_KEY6;                     /*!< (@ 0x00000018) AES Key 6.                                                 */
  __IOM uint32_t  AES_KEY7;                     /*!< (@ 0x0000001C) AES Key 7.                                                 */
} AES_KEY_Type;                                 /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CRC Registers. (CRC)
  */

typedef struct {                                /*!< (@ 0x4000F000) CRC Structure                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) CRC Control                                                */

  union {
    __IOM uint32_t DATAIN32;                    /*!< (@ 0x00000004) CRC Data Input                                             */
    __IOM uint16_t DATAIN16[2];                 /*!< (@ 0x00000004) CRC Data Input                                             */
    __IOM uint8_t DATAIN8[4];                   /*!< (@ 0x00000004) CRC Data Input                                             */
  };
  __IOM uint32_t  POLY;                         /*!< (@ 0x00000008) CRC Polynomial                                             */
  __IOM uint32_t  VAL;                          /*!< (@ 0x0000000C) Current CRC Value                                          */
} CRC_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA Controller Fully programmable, chaining capable DMA channels. (DMA)
  */

typedef struct {                                /*!< (@ 0x40028000) DMA Structure                                              */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000000) DMA Control Register.                                      */
  __IM  uint32_t  INTFL;                        /*!< (@ 0x00000004) DMA Interrupt Register.                                    */
  __IM  uint32_t  RESERVED[62];
  __IOM dma_ch_Type CH[4];                      /*!< (@ 0x00000100) DMA Channel registers.                                     */
} DMA_Type;                                     /*!< Size = 1408 (0x580)                                                       */



/* =========================================================================================================================== */
/* ================                                            FLC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash Memory Control. (FLC)
  */

typedef struct {                                /*!< (@ 0x40029000) FLC Structure                                              */
  __IOM uint32_t  FLSH_ADDR;                    /*!< (@ 0x00000000) Flash Write Address.                                       */
  __IOM uint32_t  FLSH_CLKDIV;                  /*!< (@ 0x00000004) Flash Clock Divide. The clock (PLL0) is divided
                                                                    by this value to generate a 1 MHz clock
                                                                    for Flash controller.                                      */
  __IOM uint32_t  FLSH_CTRL;                    /*!< (@ 0x00000008) Flash Control Register.                                    */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  FLSH_INTR;                    /*!< (@ 0x00000024) Flash Interrupt Register.                                  */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  FLSH_ECCDATA;                 /*!< (@ 0x0000002C) ECC Data Register.                                         */
  __IM  uint32_t  RESERVED2[4];
  __OM  uint32_t  FLSH_ACTRL;                   /*!< (@ 0x00000040) Access Control Register. Writing the ACTRL register
                                                                    with the following values in the order shown,
                                                                    allows read and write access to the system
                                                                    and user Information block: pflc-actrl =
                                                                    0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl
                                                                    = 0x9608b2c1. When unlocked, a write of
                                                                    any word will disable access to system and
                                                                    user information block. Readback of this
                                                                    register is always zero.                                   */
  __IM  uint32_t  RESERVED3[15];
  __IOM uint32_t  FLSH_WELR0;                   /*!< (@ 0x00000080) WELR0                                                      */
  __IM  uint32_t  RESERVED4;
  __IOM uint32_t  FLSH_WELR1;                   /*!< (@ 0x00000088) WELR1                                                      */
  __IM  uint32_t  RESERVED5;
  __IOM uint32_t  FLSH_RLR0;                    /*!< (@ 0x00000090) RLR0                                                       */
  __IM  uint32_t  RESERVED6;
  __IOM uint32_t  FLSH_RLR1;                    /*!< (@ 0x00000098) RLR1                                                       */
} FLC_Type;                                     /*!< Size = 156 (0x9c)                                                         */



/* =========================================================================================================================== */
/* ================                                            GCR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Global Control Registers. (GCR)
  */

typedef struct {                                /*!< (@ 0x40000000) GCR Structure                                              */
  __IOM uint32_t  SYSCTRL;                      /*!< (@ 0x00000000) System Control.                                            */
  __IOM uint32_t  RST0;                         /*!< (@ 0x00000004) Reset.                                                     */
  __IOM uint32_t  CLKCTRL;                      /*!< (@ 0x00000008) Clock Control.                                             */
  __IOM uint32_t  PM;                           /*!< (@ 0x0000000C) Power Management.                                          */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  PCLKDIV;                      /*!< (@ 0x00000018) Peripheral Clock Divider.                                  */
  __IM  uint32_t  RESERVED1[2];
  __IOM uint32_t  PCLKDIS0;                     /*!< (@ 0x00000024) Peripheral Clock Disable.                                  */
  __IOM uint32_t  MEMCTRL;                      /*!< (@ 0x00000028) Memory Clock Control Register.                             */
  __IOM uint32_t  MEMZ;                         /*!< (@ 0x0000002C) Memory Zeroize Control.                                    */
  __IM  uint32_t  RESERVED2[4];
  __IOM uint32_t  SYSST;                        /*!< (@ 0x00000040) System Status Register.                                    */
  __IOM uint32_t  RST1;                         /*!< (@ 0x00000044) Reset 1.                                                   */
  __IOM uint32_t  PCLKDIS1;                     /*!< (@ 0x00000048) Peripheral Clock Disable.                                  */
  __IOM uint32_t  EVENTEN;                      /*!< (@ 0x0000004C) Event Enable Register.                                     */
  __IM  uint32_t  REVISION;                     /*!< (@ 0x00000050) Revision Register.                                         */
  __IOM uint32_t  SYSIE;                        /*!< (@ 0x00000054) System Status Interrupt Enable Register.                   */
  __IM  uint32_t  RESERVED3[3];
  __IOM uint32_t  ECCERR;                       /*!< (@ 0x00000064) ECC Error Register                                         */
  __IOM uint32_t  ECCCED;                       /*!< (@ 0x00000068) ECC Not Double Error Detect Register                       */
  __IOM uint32_t  ECCIE;                        /*!< (@ 0x0000006C) ECC IRQ Enable Register                                    */
  __IOM uint32_t  ECCADDR;                      /*!< (@ 0x00000070) ECC Error Address Register                                 */
  __IM  uint32_t  RESERVED4[3];
  __IOM uint32_t  GPR;                          /*!< (@ 0x00000080) General Purpose Register.                                  */
} GCR_Type;                                     /*!< Size = 132 (0x84)                                                         */



/* =========================================================================================================================== */
/* ================                                            MCR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Misc Control. (MCR)
  */

typedef struct {                                /*!< (@ 0x40006C00) MCR Structure                                              */
  __IOM uint32_t  ECCEN;                        /*!< (@ 0x00000000) ECC Enable Register                                        */
  __IOM uint32_t  IPO_MTRIM;                    /*!< (@ 0x00000004) IPO Manual Register                                        */
  __IOM uint32_t  OUTEN;                        /*!< (@ 0x00000008) Output Enable Register                                     */
  __IOM uint32_t  CMP_CTRL;                     /*!< (@ 0x0000000C) Comparator Control Register.                               */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000010) Miscellaneous Control Register.                            */
  __IM  uint32_t  RESERVED[3];
  __IOM uint32_t  GPIO3_CTRL;                   /*!< (@ 0x00000020) GPIO3 Pin Control Register.                                */
} MCR_Type;                                     /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                           LPGCR                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Low Power Global Control. (LPGCR)
  */

typedef struct {                                /*!< (@ 0x40080000) LPGCR Structure                                            */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  RST;                          /*!< (@ 0x00000008) Low Power Reset Register.                                  */
  __IOM uint32_t  PCLKDIS;                      /*!< (@ 0x0000000C) Low Power Peripheral Clock Disable Register.               */
} LPGCR_Type;                                   /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIO0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Individual I/O for each GPIO (GPIO0)
  */

typedef struct {                                /*!< (@ 0x40008000) GPIO0 Structure                                            */
  __IOM uint32_t  EN0;                          /*!< (@ 0x00000000) GPIO Function Enable Register. Each bit controls
                                                                    the GPIO_EN setting for one GPIO pin on
                                                                    the associated port.                                       */
  __IOM uint32_t  EN0_SET;                      /*!< (@ 0x00000004) GPIO Set Function Enable Register. Writing a
                                                                    1 to one or more bits in this register sets
                                                                    the bits in the same positions in GPIO_EN
                                                                    to 1, without affecting other bits in that
                                                                    register.                                                  */
  __IOM uint32_t  EN0_CLR;                      /*!< (@ 0x00000008) GPIO Clear Function Enable Register. Writing
                                                                    a 1 to one or more bits in this register
                                                                    clears the bits in the same positions in
                                                                    GPIO_EN to 0, without affecting other bits
                                                                    in that register.                                          */
  __IOM uint32_t  OUTEN;                        /*!< (@ 0x0000000C) GPIO Output Enable Register. Each bit controls
                                                                    the GPIO_OUT_EN setting for one GPIO pin
                                                                    in the associated port.                                    */
  __IOM uint32_t  OUTEN_SET;                    /*!< (@ 0x00000010) GPIO Output Enable Set Function Enable Register.
                                                                    Writing a 1 to one or more bits in this
                                                                    register sets the bits in the same positions
                                                                    in GPIO_OUT_EN to 1, without affecting other
                                                                    bits in that register.                                     */
  __IOM uint32_t  OUTEN_CLR;                    /*!< (@ 0x00000014) GPIO Output Enable Clear Function Enable Register.
                                                                    Writing a 1 to one or more bits in this
                                                                    register clears the bits in the same positions
                                                                    in GPIO_OUT_EN to 0, without affecting other
                                                                    bits in that register.                                     */
  __IOM uint32_t  OUT;                          /*!< (@ 0x00000018) GPIO Output Register. Each bit controls the GPIO_OUT
                                                                    setting for one pin in the associated port.
                                                                    This register can be written either directly,
                                                                    or by using the GPIO_OUT_SET and GPIO_OUT_CLR
                                                                    registers.                                                 */
  __OM  uint32_t  OUT_SET;                      /*!< (@ 0x0000001C) GPIO Output Set. Writing a 1 to one or more bits
                                                                    in this register sets the bits in the same
                                                                    positions in GPIO_OUT to 1, without affecting
                                                                    other bits in that register.                               */
  __OM  uint32_t  OUT_CLR;                      /*!< (@ 0x00000020) GPIO Output Clear. Writing a 1 to one or more
                                                                    bits in this register clears the bits in
                                                                    the same positions in GPIO_OUT to 0, without
                                                                    affecting other bits in that register.                     */
  __IM  uint32_t  IN;                           /*!< (@ 0x00000024) GPIO Input Register. Read-only register to read
                                                                    from the logic states of the GPIO pins on
                                                                    this port.                                                 */
  __IOM uint32_t  INTMODE;                      /*!< (@ 0x00000028) GPIO Interrupt Mode Register. Each bit in this
                                                                    register controls the interrupt mode setting
                                                                    for the associated GPIO pin on this port.                  */
  __IOM uint32_t  INTPOL;                       /*!< (@ 0x0000002C) GPIO Interrupt Polarity Register. Each bit in
                                                                    this register controls the interrupt polarity
                                                                    setting for one GPIO pin in the associated
                                                                    port.                                                      */
  __IOM uint32_t  INEN;                         /*!< (@ 0x00000030) GPIO Input Enable                                          */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000034) GPIO Interrupt Enable Register. Each bit in this
                                                                    register controls the GPIO interrupt enable
                                                                    for the associated pin on the GPIO port.                   */
  __IOM uint32_t  INTEN_SET;                    /*!< (@ 0x00000038) GPIO Interrupt Enable Set. Writing a 1 to one
                                                                    or more bits in this register sets the bits
                                                                    in the same positions in GPIO_INT_EN to
                                                                    1, without affecting other bits in that
                                                                    register.                                                  */
  __IOM uint32_t  INTEN_CLR;                    /*!< (@ 0x0000003C) GPIO Interrupt Enable Clear. Writing a 1 to one
                                                                    or more bits in this register clears the
                                                                    bits in the same positions in GPIO_INT_EN
                                                                    to 0, without affecting other bits in that
                                                                    register.                                                  */
  __IM  uint32_t  INTFL;                        /*!< (@ 0x00000040) GPIO Interrupt Status Register. Each bit in this
                                                                    register contains the pending interrupt
                                                                    status for the associated GPIO pin in this
                                                                    port.                                                      */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  INTFL_CLR;                    /*!< (@ 0x00000048) GPIO Status Clear. Writing a 1 to one or more
                                                                    bits in this register clears the bits in
                                                                    the same positions in GPIO_INT_STAT to 0,
                                                                    without affecting other bits in that register.             */
  __IOM uint32_t  WKEN;                         /*!< (@ 0x0000004C) GPIO Wake Enable Register. Each bit in this register
                                                                    controls the PMU wakeup enable for the associated
                                                                    GPIO pin in this port.                                     */
  __IOM uint32_t  WKEN_SET;                     /*!< (@ 0x00000050) GPIO Wake Enable Set. Writing a 1 to one or more
                                                                    bits in this register sets the bits in the
                                                                    same positions in GPIO_WAKE_EN to 1, without
                                                                    affecting other bits in that register.                     */
  __IOM uint32_t  WKEN_CLR;                     /*!< (@ 0x00000054) GPIO Wake Enable Clear. Writing a 1 to one or
                                                                    more bits in this register clears the bits
                                                                    in the same positions in GPIO_WAKE_EN to
                                                                    0, without affecting other bits in that
                                                                    register.                                                  */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  DUALEDGE;                     /*!< (@ 0x0000005C) GPIO Interrupt Dual Edge Mode Register. Each
                                                                    bit in this register selects dual edge mode
                                                                    for the associated GPIO pin in this port.                  */
  __IOM uint32_t  PADCTRL0;                     /*!< (@ 0x00000060) GPIO Input Mode Config 1. Each bit in this register
                                                                    enables the weak pull-up for the associated
                                                                    GPIO pin in this port.                                     */
  __IOM uint32_t  PADCTRL1;                     /*!< (@ 0x00000064) GPIO Input Mode Config 2. Each bit in this register
                                                                    enables the weak pull-up for the associated
                                                                    GPIO pin in this port.                                     */
  __IOM uint32_t  EN1;                          /*!< (@ 0x00000068) GPIO Alternate Function Enable Register. Each
                                                                    bit in this register selects between primary/secondary
                                                                    functions for the associated GPIO pin in
                                                                    this port.                                                 */
  __IOM uint32_t  EN1_SET;                      /*!< (@ 0x0000006C) GPIO Alternate Function Set. Writing a 1 to one
                                                                    or more bits in this register sets the bits
                                                                    in the same positions in GPIO_EN1 to 1,
                                                                    without affecting other bits in that register.             */
  __IOM uint32_t  EN1_CLR;                      /*!< (@ 0x00000070) GPIO Alternate Function Clear. Writing a 1 to
                                                                    one or more bits in this register clears
                                                                    the bits in the same positions in GPIO_EN1
                                                                    to 0, without affecting other bits in that
                                                                    register.                                                  */
  __IOM uint32_t  EN2;                          /*!< (@ 0x00000074) GPIO Alternate Function Enable Register. Each
                                                                    bit in this register selects between primary/secondary
                                                                    functions for the associated GPIO pin in
                                                                    this port.                                                 */
  __IOM uint32_t  EN2_SET;                      /*!< (@ 0x00000078) GPIO Alternate Function 2 Set. Writing a 1 to
                                                                    one or more bits in this register sets the
                                                                    bits in the same positions in GPIO_EN2 to
                                                                    1, without affecting other bits in that
                                                                    register.                                                  */
  __IOM uint32_t  EN2_CLR;                      /*!< (@ 0x0000007C) GPIO Wake Alternate Function Clear. Writing a
                                                                    1 to one or more bits in this register clears
                                                                    the bits in the same positions in GPIO_EN2
                                                                    to 0, without affecting other bits in that
                                                                    register.                                                  */
  __IM  uint32_t  RESERVED2[10];
  __IOM uint32_t  HYSEN;                        /*!< (@ 0x000000A8) GPIO Input Hysteresis Enable.                              */
  __IOM uint32_t  SRSEL;                        /*!< (@ 0x000000AC) GPIO Slew Rate Enable Register.                            */
  __IOM uint32_t  DS0;                          /*!< (@ 0x000000B0) GPIO Drive Strength Register. Each bit in this
                                                                    register selects the drive strength for
                                                                    the associated GPIO pin in this port. Refer
                                                                    to the Datasheet for sink/source current
                                                                    of GPIO pins in each mode.                                 */
  __IOM uint32_t  DS1;                          /*!< (@ 0x000000B4) GPIO Drive Strength 1 Register. Each bit in this
                                                                    register selects the drive strength for
                                                                    the associated GPIO pin in this port. Refer
                                                                    to the Datasheet for sink/source current
                                                                    of GPIO pins in each mode.                                 */
  __IOM uint32_t  PS;                           /*!< (@ 0x000000B8) GPIO Pull Select Mode.                                     */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  VSSEL;                        /*!< (@ 0x000000C0) GPIO Voltage Select.                                       */
} GPIO_Type;                                   /*!< Size = 196 (0xc4)                                                         */



/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Inter-Integrated Circuit. (I2C0)
  */

typedef struct {                                /*!< (@ 0x4001D000) I2C0 Structure                                             */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) Control Register0.                                         */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000004) Status Register.                                           */
  __IOM uint32_t  INTFL0;                       /*!< (@ 0x00000008) Interrupt Status Register.                                 */
  __IOM uint32_t  INTEN0;                       /*!< (@ 0x0000000C) Interrupt Enable Register.                                 */
  __IOM uint32_t  INTFL1;                       /*!< (@ 0x00000010) Interrupt Status Register 1.                               */
  __IOM uint32_t  INTEN1;                       /*!< (@ 0x00000014) Interrupt Staus Register 1.                                */
  __IOM uint32_t  FIFOLEN;                      /*!< (@ 0x00000018) FIFO Configuration Register.                               */
  __IOM uint32_t  RXCTRL0;                      /*!< (@ 0x0000001C) Receive Control Register 0.                                */
  __IOM uint32_t  RXCTRL1;                      /*!< (@ 0x00000020) Receive Control Register 1.                                */
  __IOM uint32_t  TXCTRL0;                      /*!< (@ 0x00000024) Transmit Control Register 0.                               */
  __IOM uint32_t  TXCTRL1;                      /*!< (@ 0x00000028) Transmit Control Register 1.                               */
  __IOM uint32_t  FIFO;                         /*!< (@ 0x0000002C) Data Register.                                             */
  __IOM uint32_t  MSTCTRL;                      /*!< (@ 0x00000030) Master Control Register.                                   */
  __IOM uint32_t  CLKLO;                        /*!< (@ 0x00000034) Clock Low Register.                                        */
  __IOM uint32_t  CLKHI;                        /*!< (@ 0x00000038) Clock high Register.                                       */
  __IOM uint32_t  HSCLK;                        /*!< (@ 0x0000003C) Clock high Register.                                       */
  __IOM uint32_t  TIMEOUT;                      /*!< (@ 0x00000040) Timeout Register                                           */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  DMA;                          /*!< (@ 0x00000048) DMA Register.                                              */
  __IOM uint32_t  SLAVE;                        /*!< (@ 0x0000004C) Slave Address Register.                                    */
} I2C_Type;                                    /*!< Size = 80 (0x50)                                                          */



/* =========================================================================================================================== */
/* ================                                            I2S                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Inter-IC Sound Interface. (I2S)
  */

typedef struct {                                /*!< (@ 0x40060000) I2S Structure                                              */
  __IOM uint32_t  CTRL0CH0;                     /*!< (@ 0x00000000) Global mode channel.                                       */
  __IM  uint32_t  RESERVED[3];
  __IOM uint32_t  CTRL1CH0;                     /*!< (@ 0x00000010) Local channel Setup.                                       */
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  FILTCH0;                      /*!< (@ 0x00000020) Filter.                                                    */
  __IM  uint32_t  RESERVED2[3];
  __IOM uint32_t  DMACH0;                       /*!< (@ 0x00000030) DMA Control.                                               */
  __IM  uint32_t  RESERVED3[3];
  __IOM uint32_t  FIFOCH0;                      /*!< (@ 0x00000040) I2S Fifo.                                                  */
  __IM  uint32_t  RESERVED4[3];
  __IOM uint32_t  INTFL;                        /*!< (@ 0x00000050) ISR Status.                                                */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000054) Interrupt Enable.                                          */
  __IOM uint32_t  EXTSETUP;                     /*!< (@ 0x00000058) Ext Control.                                               */
  __IOM uint32_t  WKEN;                         /*!< (@ 0x0000005C) Wakeup Enable.                                             */
  __IOM uint32_t  WKFL;                         /*!< (@ 0x00000060) Wakeup Flags.                                              */
} I2S_Type;                                     /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                            OWM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief 1-Wire Master Interface. (OWM)
  */

typedef struct {                                /*!< (@ 0x4003D000) OWM Structure                                              */
  __IOM uint32_t  CFG;                          /*!< (@ 0x00000000) 1-Wire Master Configuration.                               */
  __IOM uint32_t  CLK_DIV_1US;                  /*!< (@ 0x00000004) 1-Wire Master Clock Divisor.                               */
  __IOM uint32_t  CTRL_STAT;                    /*!< (@ 0x00000008) 1-Wire Master Control/Status.                              */
  __IOM uint32_t  DATA;                         /*!< (@ 0x0000000C) 1-Wire Master Data Buffer.                                 */
  __IOM uint32_t  INTFL;                        /*!< (@ 0x00000010) 1-Wire Master Interrupt Flags.                             */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000014) 1-Wire Master Interrupt Enables.                           */
} OWM_Type;                                     /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                            PTG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Pulse Train Generation (PTG)
  */

typedef struct {                                /*!< (@ 0x4003C000) PTG Structure                                              */
  __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000000) Global Enable/Disable Controls for All Pulse
                                                                    Trains                                                     */
  __IOM uint32_t  RESYNC;                       /*!< (@ 0x00000004) Global Resync (All Pulse Trains) Control                   */
  __IOM uint32_t  INTFL;                        /*!< (@ 0x00000008) Pulse Train Interrupt Flags                                */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x0000000C) Pulse Train Interrupt Enable/Disable                       */
  __OM  uint32_t  SAFE_EN;                      /*!< (@ 0x00000010) Pulse Train Global Safe Enable.                            */
  __OM  uint32_t  SAFE_DIS;                     /*!< (@ 0x00000014) Pulse Train Global Safe Disable.                           */
} PTG_Type;                                     /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                            PT                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Pulse Train (PT)
  */

typedef struct {                                /*!< (@ 0x4003C020) PT Structure                                               */
  __IOM uint32_t  RATE_LENGTH;                  /*!< (@ 0x00000000) Pulse Train Configuration                                  */
  __IOM uint32_t  TRAIN;                        /*!< (@ 0x00000004) Write the repeating bit pattern that is shifted
                                                                    out, LSB first, when configured in Pulse
                                                                    Train mode. See PT_RATE_LENGTH.mode for
                                                                    setting the length.                                        */
  __IOM uint32_t  LOOP;                         /*!< (@ 0x00000008) Pulse Train Loop Count                                     */
  __IOM uint32_t  RESTART;                      /*!< (@ 0x0000000C) Pulse Train Auto-Restart Configuration.                    */
} PT_Type;                                      /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           ICC0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Instruction Cache Controller Registers (ICC0)
  */

typedef struct {                                /*!< (@ 0x4002A000) ICC0 Structure                                             */
  __IM  uint32_t  INFO;                         /*!< (@ 0x00000000) Cache ID Register.                                         */
  __IM  uint32_t  SZ;                           /*!< (@ 0x00000004) Memory Configuration Register.                             */
  __IM  uint32_t  RESERVED[62];
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000100) Cache Control and Status Register.                         */
  __IM  uint32_t  RESERVED1[383];
  __IOM uint32_t  INVALIDATE;                   /*!< (@ 0x00000700) Invalidate All Registers.                                  */
} ICC_Type;                                     /*!< Size = 1796 (0x704)                                                       */



/* =========================================================================================================================== */
/* ================                                          PWRSEQ                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Power Sequencer / Low Power Control Register. (PWRSEQ)
  */

typedef struct {                                /*!< (@ 0x40006800) PWRSEQ Structure                                           */
  __IOM uint32_t  LPCN;                         /*!< (@ 0x00000000) Low Power Control Register.                                */
  __IOM uint32_t  LPWKST0;                      /*!< (@ 0x00000004) Low Power I/O Wakeup Status Register 0. This
                                                                    register indicates the low power wakeup
                                                                    status for GPIO0.                                          */
  __IOM uint32_t  LPWKEN0;                      /*!< (@ 0x00000008) Low Power I/O Wakeup Enable Register 0. This
                                                                    register enables low power wakeup functionality
                                                                    for GPIO0.                                                 */
  __IOM uint32_t  LPWKST1;                      /*!< (@ 0x0000000C) Low Power I/O Wakeup Status Register 1. This
                                                                    register indicates the low power wakeup
                                                                    status for GPIO1.                                          */
  __IOM uint32_t  LPWKEN1;                      /*!< (@ 0x00000010) Low Power I/O Wakeup Enable Register 1. This
                                                                    register enables low power wakeup functionality
                                                                    for GPIO1.                                                 */
  __IOM uint32_t  LPWKST2;                      /*!< (@ 0x00000014) Low Power I/O Wakeup Status Register 2. This
                                                                    register indicates the low power wakeup
                                                                    status for GPIO2.                                          */
  __IOM uint32_t  LPWKEN2;                      /*!< (@ 0x00000018) Low Power I/O Wakeup Enable Register 2. This
                                                                    register enables low power wakeup functionality
                                                                    for GPIO2.                                                 */
  __IOM uint32_t  LPWKST3;                      /*!< (@ 0x0000001C) Low Power I/O Wakeup Status Register 3. This
                                                                    register indicates the low power wakeup
                                                                    status for GPIO3.                                          */
  __IOM uint32_t  LPWKEN3;                      /*!< (@ 0x00000020) Low Power I/O Wakeup Enable Register 3. This
                                                                    register enables low power wakeup functionality
                                                                    for GPIO3.                                                 */
  __IM  uint32_t  RESERVED[3];
  __IOM uint32_t  LPPWST;                       /*!< (@ 0x00000030) Low Power Peripheral Wakeup Status Register.               */
  __IOM uint32_t  LPPWEN;                       /*!< (@ 0x00000034) Low Power Peripheral Wakeup Enable Register.               */
  __IM  uint32_t  RESERVED1[4];
  __IOM uint32_t  GP0;                          /*!< (@ 0x00000048) General Purpose Register 0                                 */
  __IOM uint32_t  GP1;                          /*!< (@ 0x0000004C) General Purpose Register 1                                 */
} PWRSEQ_Type;                                  /*!< Size = 80 (0x50)                                                          */



/* =========================================================================================================================== */
/* ================                                           LPCMP                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Low Power Comparator (LPCMP)
  */

typedef struct {                                /*!< (@ 0x40088000) LPCMP Structure                                            */
  __IOM uint32_t  CTRL[3];                      /*!< (@ 0x00000000) Comparator Control Register.                               */
} LPCMP_Type;                                   /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real Time Clock and Alarm. (RTC)
  */

typedef struct {                                /*!< (@ 0x40106000) RTC Structure                                              */
  __IOM uint32_t  SEC;                          /*!< (@ 0x00000000) RTC Second Counter. This register contains the
                                                                    32-bit second counter.                                     */
  __IOM uint32_t  SSEC;                         /*!< (@ 0x00000004) RTC Sub-second Counter. This counter increments
                                                                    at 256Hz. RTC_SEC is incremented when this
                                                                    register rolls over from 0xFF to 0x00.                     */
  __IOM uint32_t  TODA;                         /*!< (@ 0x00000008) Time-of-day Alarm.                                         */
  __IOM uint32_t  SSECA;                        /*!< (@ 0x0000000C) RTC sub-second alarm. This register contains
                                                                    the reload value for the sub-second alarm.                 */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000010) RTC Control Register.                                      */
  __IOM uint32_t  TRIM;                         /*!< (@ 0x00000014) RTC Trim Register.                                         */
  __IOM uint32_t  OSCCTRL;                      /*!< (@ 0x00000018) RTC Oscillator Control Register.                           */
} RTC_Type;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief SPI peripheral. (SPI0)
  */

typedef struct {                                /*!< (@ 0x40046000) SPI0 Structure                                             */

  union {
    __IOM uint32_t FIFO32;                      /*!< (@ 0x00000000) Register for reading and writing the FIFO.                 */
    __IOM uint16_t FIFO16[2];                   /*!< (@ 0x00000000) Register for reading and writing the FIFO.                 */
    __IOM uint8_t FIFO8[4];                     /*!< (@ 0x00000000) Register for reading and writing the FIFO.                 */
  };
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x00000004) Register for controlling SPI peripheral.                   */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x00000008) Register for controlling SPI peripheral.                   */
  __IOM uint32_t  CTRL2;                        /*!< (@ 0x0000000C) Register for controlling SPI peripheral.                   */
  __IOM uint32_t  SSTIME;                       /*!< (@ 0x00000010) Register for controlling SPI peripheral/Slave
                                                                    Select Timing.                                             */
  __IOM uint32_t  CLKCTRL;                      /*!< (@ 0x00000014) Register for controlling SPI clock rate.                   */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  DMA;                          /*!< (@ 0x0000001C) Register for controlling DMA.                              */
  __IOM uint32_t  INTFL;                        /*!< (@ 0x00000020) Register for reading and clearing interrupt flags.
                                                                    All bits are write 1 to clear.                             */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000024) Register for enabling interrupts.                          */
  __IOM uint32_t  WKFL;                         /*!< (@ 0x00000028) Register for wake up flags. All bits in this
                                                                    register are write 1 to clear.                             */
  __IOM uint32_t  WKEN;                         /*!< (@ 0x0000002C) Register for wake up enable.                               */
  __IM  uint32_t  STAT;                         /*!< (@ 0x00000030) SPI Status register.                                       */
} SPI_Type;                                    /*!< Size = 52 (0x34)                                                          */



/* =========================================================================================================================== */
/* ================                                            TMR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Low-Power Configurable Timer (TMR)
  */

typedef struct {                                /*!< (@ 0x40010000) TMR Structure                                              */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000000) Timer Counter Register.                                    */
  __IOM uint32_t  CMP;                          /*!< (@ 0x00000004) Timer Compare Register.                                    */
  __IOM uint32_t  PWM;                          /*!< (@ 0x00000008) Timer PWM Register.                                        */
  __IOM uint32_t  INTFL;                        /*!< (@ 0x0000000C) Timer Interrupt Status Register.                           */
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x00000010) Timer Control Register.                                    */
  __IOM uint32_t  NOLCMP;                       /*!< (@ 0x00000014) Timer Non-Overlapping Compare Register.                    */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x00000018) Timer Configuration Register.                              */
  __IOM uint32_t  WKFL;                         /*!< (@ 0x0000001C) Timer Wakeup Status Register.                              */
} TMR_Type;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                           TRNG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Random Number Generator. (TRNG)
  */

typedef struct {                                /*!< (@ 0x4004D000) TRNG Structure                                             */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) TRNG Control Register.                                     */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000004) Data. The content of this register is valid only
                                                                    when RNG_IS = 1. When TRNG is disabled,
                                                                    read returns 0x0000 0000.                                  */
  __IM  uint32_t  DATA;                         /*!< (@ 0x00000008) Data. The content of this register is valid only
                                                                    when RNG_IS = 1. When TRNG is disabled,
                                                                    read returns 0x0000 0000.                                  */
} TRNG_Type;                                    /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief UART Low Power Registers (UART)
  */

typedef struct {                                /*!< (@ 0x40042000) UART Structure                                             */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) Control register                                           */
  __IM  uint32_t  STATUS;                       /*!< (@ 0x00000004) Status register                                            */
  __IOM uint32_t  INT_EN;                       /*!< (@ 0x00000008) Interrupt Enable control register                          */
  __IOM uint32_t  INT_FL;                       /*!< (@ 0x0000000C) Interrupt status flags Control register                    */
  __IOM uint32_t  CLKDIV;                       /*!< (@ 0x00000010) Clock Divider register                                     */
  __IOM uint32_t  OSR;                          /*!< (@ 0x00000014) Over Sampling Rate register                                */
  __IOM uint32_t  TXPEEK;                       /*!< (@ 0x00000018) TX FIFO Output Peek register                               */
  __IOM uint32_t  PNR;                          /*!< (@ 0x0000001C) Pin register                                               */
  __IOM uint32_t  FIFO;                         /*!< (@ 0x00000020) FIFO Read/Write register                                   */
  __IM  uint32_t  RESERVED[3];
  __IOM uint32_t  DMA;                          /*!< (@ 0x00000030) DMA Configuration register                                 */
  __IOM uint32_t  WKEN;                         /*!< (@ 0x00000034) Wake up enable Control register                            */
  __IOM uint32_t  WKFL;                         /*!< (@ 0x00000038) Wake up Flags register                                     */
} UART_Type;                                    /*!< Size = 60 (0x3c)                                                          */



/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Windowed Watchdog Timer (WDT)
  */

typedef struct {                                /*!< (@ 0x40003000) WDT Structure                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) Watchdog Timer Control Register.                           */
  __OM  uint32_t  RST;                          /*!< (@ 0x00000004) Windowed Watchdog Timer Reset Register.                    */
  __IOM uint32_t  CLKSEL;                       /*!< (@ 0x00000008) Windowed Watchdog Timer Clock Select Register.             */
  __IM  uint32_t  CNT;                          /*!< (@ 0x0000000C) Windowed Watchdog Timer Count Register.                    */
} WDT_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           SIMO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Single Inductor Multiple Output Switching Converter (SIMO)
  */

typedef struct {                                /*!< (@ 0x40004400) SIMO Structure                                             */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  VREGO_A;                      /*!< (@ 0x00000004) Buck Voltage Regulator A Control Register                  */
  __IOM uint32_t  VREGO_B;                      /*!< (@ 0x00000008) Buck Voltage Regulator B Control Register                  */
  __IOM uint32_t  VREGO_C;                      /*!< (@ 0x0000000C) Buck Voltage Regulator C Control Register                  */
  __IOM uint32_t  VREGO_D;                      /*!< (@ 0x00000010) Buck Voltage Regulator D Control Register                  */
  __IOM uint32_t  IPKA;                         /*!< (@ 0x00000014) High Side FET Peak Current VREGO_A/VREGO_B Register        */
  __IOM uint32_t  IPKB;                         /*!< (@ 0x00000018) High Side FET Peak Current VREGO_C/VREGO_D Register        */
  __IOM uint32_t  MAXTON;                       /*!< (@ 0x0000001C) Maximum High Side FET Time On Register                     */
  __IM  uint32_t  ILOAD_A;                      /*!< (@ 0x00000020) Buck Cycle Count VREGO_A Register                          */
  __IM  uint32_t  ILOAD_B;                      /*!< (@ 0x00000024) Buck Cycle Count VREGO_B Register                          */
  __IM  uint32_t  ILOAD_C;                      /*!< (@ 0x00000028) Buck Cycle Count VREGO_C Register                          */
  __IM  uint32_t  ILOAD_D;                      /*!< (@ 0x0000002C) Buck Cycle Count VREGO_D Register                          */
  __IOM uint32_t  BUCK_ALERT_THR_A;             /*!< (@ 0x00000030) Buck Cycle Count Alert VERGO_A Register                    */
  __IOM uint32_t  BUCK_ALERT_THR_B;             /*!< (@ 0x00000034) Buck Cycle Count Alert VERGO_B Register                    */
  __IOM uint32_t  BUCK_ALERT_THR_C;             /*!< (@ 0x00000038) Buck Cycle Count Alert VERGO_C Register                    */
  __IOM uint32_t  BUCK_ALERT_THR_D;             /*!< (@ 0x0000003C) Buck Cycle Count Alert VERGO_D Register                    */
  __IM  uint32_t  BUCK_OUT_READY;               /*!< (@ 0x00000040) Buck Regulator Output Ready Register                       */
  __IM  uint32_t  ZERO_CROSS_CAL_A;             /*!< (@ 0x00000044) Zero Cross Calibration VERGO_A Register                    */
  __IM  uint32_t  ZERO_CROSS_CAL_B;             /*!< (@ 0x00000048) Zero Cross Calibration VERGO_B Register                    */
  __IM  uint32_t  ZERO_CROSS_CAL_C;             /*!< (@ 0x0000004C) Zero Cross Calibration VERGO_C Register                    */
  __IM  uint32_t  ZERO_CROSS_CAL_D;             /*!< (@ 0x00000050) Zero Cross Calibration VERGO_D Register                    */
} SIMO_Type;                                    /*!< Size = 84 (0x54)                                                          */



/* =========================================================================================================================== */
/* ================                                           SEMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources.
                                     The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software
                                     architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be

                                     modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. (SEMA)
  */

typedef struct {                                /*!< (@ 0x4003E000) SEMA Structure                                             */
  __IOM uint32_t  SEMAPHORES[8];                /*!< (@ 0x00000000) Read to test and set, returns prior value. Write
                                                                    0 to clear semaphore.                                      */
  __IM  uint32_t  RESERVED[8];
  __IOM uint32_t  irq0;                         /*!< (@ 0x00000040) Semaphore IRQ0 register.                                   */
  __IOM uint32_t  mail0;                        /*!< (@ 0x00000044) Semaphore Mailbox 0 register.                              */
  __IOM uint32_t  irq1;                         /*!< (@ 0x00000048) Semaphore IRQ1 register.                                   */
  __IOM uint32_t  mail1;                        /*!< (@ 0x0000004C) Semaphore Mailbox 1 register.                              */
  __IM  uint32_t  RESERVED1[44];
  __IOM uint32_t  status;                       /*!< (@ 0x00000100) Semaphore status bits. 0 indicates the semaphore
                                                                    is free, 1 indicates taken.                                */
} SEMA_Type;                                    /*!< Size = 260 (0x104)                                                        */



/* =========================================================================================================================== */
/* ================                                            FCR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Function Control Register. (FCR)
  */

typedef struct {                                /*!< (@ 0x40000800) FCR Structure                                              */
  __IOM uint32_t  FCTRL0;                       /*!< (@ 0x00000000) Function Control 0.                                        */
  __IOM uint32_t  AUTOCAL0;                     /*!< (@ 0x00000004) Automatic Calibration 0.                                   */
  __IOM uint32_t  AUTOCAL1;                     /*!< (@ 0x00000008) Automatic Calibration 1.                                   */
  __IOM uint32_t  AUTOCAL2;                     /*!< (@ 0x0000000C) Automatic Calibration 2                                    */
  __IOM uint32_t  URVBOOTADDR;                  /*!< (@ 0x00000010) RISC-V Boot Address.                                       */
  __IOM uint32_t  URVCTRL;                      /*!< (@ 0x00000014) RISC-V Control Register.                                   */
} FCR_Type;                                     /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                           GCFR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Global Control Function Register. (GCFR)
  */

typedef struct {                                /*!< (@ 0x40005800) GCFR Structure                                             */
  __IOM uint32_t  REG0;                         /*!< (@ 0x00000000) Register 0.                                                */
  __IOM uint32_t  REG1;                         /*!< (@ 0x00000004) Register 1.                                                */
  __IOM uint32_t  REG2;                         /*!< (@ 0x00000008) Register 2.                                                */
  __IOM uint32_t  REG3;                         /*!< (@ 0x0000000C) Register 3.                                                */
} GCFR_Type;                                    /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            SIR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System Initialization Registers. (SIR)
  */

typedef struct {                                /*!< (@ 0x40000400) SIR Structure                                              */
  __IM  uint32_t  SISTAT;                       /*!< (@ 0x00000000) System Initialization Status Register.                     */
  __IM  uint32_t  ADDR;                         /*!< (@ 0x00000004) Read-only field set by the SIB block if a CRC
                                                                    error occurs during the read of the OTP
                                                                    memory. Contains the failing address in
                                                                    OTP memory (when CRCERR equals 1).                         */
  __IM  uint32_t  RESERVED[62];
  __IM  uint32_t  FSTAT;                        /*!< (@ 0x00000100) funcstat register.                                         */
  __IM  uint32_t  SFSTAT;                       /*!< (@ 0x00000104) Security function status register.                         */
} SIR_Type;                                     /*!< Size = 264 (0x108)                                                        */



/* =========================================================================================================================== */
/* ================                                          TRIMSIR                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Trim System Initilazation Registers (TRIMSIR)
  */

typedef struct {                                /*!< (@ 0x40005400) TRIMSIR Structure                                          */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  RTC;                          /*!< (@ 0x00000008) RTC Trim System Initialization Register.                   */
  __IM  uint32_t  RESERVED1[10];
  __IM  uint32_t  SIMO;                         /*!< (@ 0x00000034) SIMO Trim System Initialization Register.                  */
  __IM  uint32_t  RESERVED2;
  __IM  uint32_t  IPOLO;                        /*!< (@ 0x0000003C) IPO Low Trim System Initialization Register.               */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000040) Control Trim System Initialization Register.               */
  __IOM uint32_t  INRO;                         /*!< (@ 0x00000044) RTC Trim System Initialization Register.                   */
} TRIMSIR_Type;                                 /*!< Size = 72 (0x48)                                                          */



/* =========================================================================================================================== */
/* ================                                            DVS                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Dynamic Voltage Scaling (DVS)
  */

typedef struct {                                /*!< (@ 0x40003C00) DVS Structure                                              */
  __IOM uint32_t  DVS_CTL;                      /*!< (@ 0x00000000) Control Register                                           */
  __IOM uint32_t  DVS_STAT;                     /*!< (@ 0x00000004) Status Fields                                              */
  __IOM uint32_t  DVS_DIRECT;                   /*!< (@ 0x00000008) Direct control of target voltage                           */
  __IOM uint32_t  DVS_MON;                      /*!< (@ 0x0000000C) Monitor Delay                                              */
  __IOM uint32_t  DVS_ADJ_UP;                   /*!< (@ 0x00000010) Up Delay Register                                          */
  __IOM uint32_t  DVS_ADJ_DWN;                  /*!< (@ 0x00000014) Down Delay Register                                        */
  __IOM uint32_t  DVS_THRES_CMP;                /*!< (@ 0x00000018) Up Delay Register                                          */
} DVS_Type;                                     /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                         CAMERAIF                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Parallel Camera Interface. (CAMERAIF)
  */

typedef struct {                                /*!< (@ 0x4000E000) CAMERAIF Structure                                         */
  __IOM uint32_t  VER;                          /*!< (@ 0x00000000) Hardware Version.                                          */
  __IOM uint32_t  FIFO_SIZE;                    /*!< (@ 0x00000004) FIFO Depth.                                                */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000008) Control Register.                                          */
  __IOM uint32_t  INT_EN;                       /*!< (@ 0x0000000C) Interupt Enable Register.                                  */
  __IOM uint32_t  INT_FL;                       /*!< (@ 0x00000010) Interupt Flag Register.                                    */
  __IOM uint32_t  DS_TIMING_CODES;              /*!< (@ 0x00000014) DS Timing Code Register.                                   */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  FIFO_DATA;                    /*!< (@ 0x00000030) FIFO DATA Register.                                        */
} CAMERAIF_Type;                                /*!< Size = 52 (0x34)                                                          */



/* =========================================================================================================================== */
/* ================                                            WUT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief 32-bit reloadable timer that can be used for timing and wakeup. (WUT)
  */

typedef struct {                                /*!< (@ 0x40006400) WUT Structure                                              */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000000) Count. This register stores the current timer
                                                                    count.                                                     */
  __IOM uint32_t  CMP;                          /*!< (@ 0x00000004) Compare. This register stores the compare value,
                                                                    which is used to set the maximum count value
                                                                    to initiate a reload of the timer to 0x0001.               */
  __IOM uint32_t  PWM;                          /*!< (@ 0x00000008) PWM. This register stores the value that is compared
                                                                    to the current timer count.                                */
  __IOM uint32_t  INTR;                         /*!< (@ 0x0000000C) Clear Interrupt. Writing a value (0 or 1) to
                                                                    a bit in this register clears the associated
                                                                    interrupt.                                                 */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000010) Timer Control Register.                                    */
  __IOM uint32_t  NOLCMP;                       /*!< (@ 0x00000014) Timer Non-Overlapping Compare Register.                    */
  __IOM uint32_t  PRESET;                       /*!< (@ 0x00000018) Preset register.                                           */
  __IOM uint32_t  RELOAD;                       /*!< (@ 0x0000001C) Reload register.                                           */
  __IOM uint32_t  SNAPSHOT;                     /*!< (@ 0x00000020) Snapshot register.                                         */
} WUT_Type;                                     /*!< Size = 36 (0x24)                                                          */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define ADC_BASE                    0x40034000UL
#define AES_BASE                    0x40074000UL
#define AES_KEY_BASE                0x40078000UL
#define CRC_BASE                    0x4000F000UL
#define DMA_BASE                    0x40028000UL
#define FLC_BASE                    0x40029000UL
#define GCR_BASE                    0x40000000UL
#define MCR_BASE                    0x40006C00UL
#define LPGCR_BASE                  0x40080000UL

#define GPIO0_BASE                  0x40008000UL
#define GPIO1_BASE                  0x40009000UL
#define GPIO2_BASE                  0x40080400UL
#define GPIO3_BASE                  0x40080600UL

#define I2C0_BASE                   0x4001D000UL
#define I2C1_BASE                   0x4001E000UL
#define I2C2_BASE                   0x4001F000UL
#define I2S_BASE                    0x40060000UL
#define OWM_BASE                    0x4003D000UL
#define PTG_BASE                    0x4003C000UL
#define PT0_BASE                    0x4003C020UL
#define PT1_BASE                    0x4003C040UL
#define PT2_BASE                    0x4003C060UL
#define PT3_BASE                    0x4003C080UL
#define PT4_BASE                    0x00000000UL
#define ICC0_BASE                   0x4002A000UL
#define ICC1_BASE                   0x4002A800UL
#define PWRSEQ_BASE                 0x40006800UL
#define LPCMP_BASE                  0x40088000UL
#define RTC_BASE                    0x40106000UL
#define SPI0_BASE                   0x40046000UL
#define SPI1_BASE                   0x40047000UL
#define SPI2_BASE                   0x40048000UL

#define TMR0_BASE                   0x40010000UL
#define TMR1_BASE                   0x40011000UL
#define TMR2_BASE                   0x40012000UL
#define TMR3_BASE                   0x40013000UL
#define TMR4_BASE                   0x40080C00UL
#define TMR5_BASE                   0x40081000UL

#define TRNG_BASE                   0x4004D000UL
#define UART0_BASE                  0x40042000UL
#define UART1_BASE                  0x40043000UL
#define UART2_BASE                  0x40044000UL
#define UART3_BASE                  0x40145000UL
#define WDT0_BASE                   0x40003000UL
#define WDT1_BASE                   0x40080800UL
#define SIMO_BASE                   0x40004400UL
#define SEMA_BASE                   0x4003E000UL
#define FCR_BASE                    0x40000800UL
#define GCFR_BASE                   0x40005800UL
#define SIR_BASE                    0x40000400UL
#define TRIMSIR_BASE                0x40005400UL
#define DVS_BASE                    0x40003C00UL
#define CAMERAIF_BASE               0x4000E000UL
#define WUT_BASE                    0x40006400UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define ADC                         ((ADC_Type*)               ADC_BASE)
#define AES                         ((AES_Type*)               AES_BASE)
#define AES_KEY                     ((AES_KEY_Type*)           AES_KEY_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define DMA                         ((DMA_Type*)               DMA_BASE)
#define FLC                         ((FLC_Type*)               FLC_BASE)
#define GCR                         ((GCR_Type*)               GCR_BASE)
#define MCR                         ((MCR_Type*)               MCR_BASE)
#define LPGCR                       ((LPGCR_Type*)             LPGCR_BASE)
#define GPIO0                       ((GPIO_Type*)             GPIO0_BASE)
#define GPIO1                       ((GPIO_Type*)             GPIO1_BASE)
#define GPIO2                       ((GPIO_Type*)             GPIO2_BASE)
#define GPIO3                       ((GPIO_Type*)             GPIO3_BASE)
#define I2C0                        ((I2C_Type*)              I2C0_BASE)
#define I2C1                        ((I2C_Type*)              I2C1_BASE)
#define I2C2                        ((I2C_Type*)              I2C2_BASE)
#define I2S                         ((I2S_Type*)               I2S_BASE)
#define OWM                         ((OWM_Type*)               OWM_BASE)
#define PTG                         ((PTG_Type*)               PTG_BASE)
#define PT0                         ((PT_Type*)                PT0_BASE)
#define PT1                         ((PT_Type*)                PT1_BASE)
#define PT2                         ((PT_Type*)                PT2_BASE)
#define PT3                         ((PT_Type*)                PT3_BASE)
#define PT4                         ((PT_Type*)                PT4_BASE)
#define ICC0                        ((ICC_Type*)              ICC0_BASE)
#define ICC1                        ((ICC_Type*)              ICC1_BASE)
#define PWRSEQ                      ((PWRSEQ_Type*)            PWRSEQ_BASE)
#define LPCMP                       ((LPCMP_Type*)             LPCMP_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define SPI0                        ((SPI_Type*)              SPI0_BASE)
#define SPI1                        ((SPI_Type*)              SPI1_BASE)
#define SPI2                        ((SPI_Type*)              SPI2_BASE)
#define TMR                         ((TMR_Type*)               TMR_BASE)
#define TMR1                        ((TMR_Type*)               TMR1_BASE)
#define TMR2                        ((TMR_Type*)               TMR2_BASE)
#define TMR3                        ((TMR_Type*)               TMR3_BASE)
#define TMR4                        ((TMR_Type*)               TMR4_BASE)
#define TMR5                        ((TMR_Type*)               TMR5_BASE)
#define TRNG                        ((TRNG_Type*)              TRNG_BASE)
#define UART0                       ((UART_Type*)              UART0_BASE)
#define UART1                       ((UART_Type*)              UART1_BASE)
#define UART2                       ((UART_Type*)              UART2_BASE)
#define UART3                       ((UART_Type*)              UART3_BASE)
#define WDT0                        ((WDT_Type*)               WDT0_BASE)
#define WDT1                        ((WDT_Type*)               WDT1_BASE)
#define SIMO                        ((SIMO_Type*)              SIMO_BASE)
#define SEMA                        ((SEMA_Type*)              SEMA_BASE)
#define FCR                         ((FCR_Type*)               FCR_BASE)
#define GCFR                        ((GCFR_Type*)              GCFR_BASE)
#define SIR                         ((SIR_Type*)               SIR_BASE)
#define TRIMSIR                     ((TRIMSIR_Type*)           TRIMSIR_BASE)
#define DVS                         ((DVS_Type*)               DVS_BASE)
#define CAMERAIF                    ((CAMERAIF_Type*)          CAMERAIF_BASE)
#define WUT                         ((WUT_Type*)               WUT_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                 Pos/Mask Cluster Section                                  ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_clusters
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            DMA                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define DMA_DMA_CH_CTRL_EN_SHIFT            (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_DMA_CH_CTRL_EN_MASK             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_DMA_CH_CTRL_RLDEN_SHIFT         (1UL)                     /*!< RLDEN (Bit 1)                                         */
#define DMA_DMA_CH_CTRL_RLDEN_MASK          (0x2UL)                   /*!< RLDEN (Bitfield-Mask: 0x01)                           */
#define DMA_DMA_CH_CTRL_PRI_SHIFT           (2UL)                     /*!< PRI (Bit 2)                                           */
#define DMA_DMA_CH_CTRL_PRI_MASK            (0xcUL)                   /*!< PRI (Bitfield-Mask: 0x03)                             */
#define DMA_DMA_CH_CTRL_REQUEST_SHIFT       (4UL)                     /*!< REQUEST (Bit 4)                                       */
#define DMA_DMA_CH_CTRL_REQUEST_MASK        (0x3f0UL)                 /*!< REQUEST (Bitfield-Mask: 0x3f)                         */
#define DMA_DMA_CH_CTRL_TO_WAIT_SHIFT       (10UL)                    /*!< TO_WAIT (Bit 10)                                      */
#define DMA_DMA_CH_CTRL_TO_WAIT_MASK        (0x400UL)                 /*!< TO_WAIT (Bitfield-Mask: 0x01)                         */
#define DMA_DMA_CH_CTRL_TO_PER_SHIFT        (11UL)                    /*!< TO_PER (Bit 11)                                       */
#define DMA_DMA_CH_CTRL_TO_PER_MASK         (0x3800UL)                /*!< TO_PER (Bitfield-Mask: 0x07)                          */
#define DMA_DMA_CH_CTRL_TO_CLKDIV_SHIFT     (14UL)                    /*!< TO_CLKDIV (Bit 14)                                    */
#define DMA_DMA_CH_CTRL_TO_CLKDIV_MASK      (0xc000UL)                /*!< TO_CLKDIV (Bitfield-Mask: 0x03)                       */
#define DMA_DMA_CH_CTRL_SRCWD_SHIFT         (16UL)                    /*!< SRCWD (Bit 16)                                        */
#define DMA_DMA_CH_CTRL_SRCWD_MASK          (0x30000UL)               /*!< SRCWD (Bitfield-Mask: 0x03)                           */
#define DMA_DMA_CH_CTRL_SRCINC_SHIFT        (18UL)                    /*!< SRCINC (Bit 18)                                       */
#define DMA_DMA_CH_CTRL_SRCINC_MASK         (0x40000UL)               /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_CTRL_DSTWD_SHIFT         (20UL)                    /*!< DSTWD (Bit 20)                                        */
#define DMA_DMA_CH_CTRL_DSTWD_MASK          (0x300000UL)              /*!< DSTWD (Bitfield-Mask: 0x03)                           */
#define DMA_DMA_CH_CTRL_DSTINC_SHIFT        (22UL)                    /*!< DSTINC (Bit 22)                                       */
#define DMA_DMA_CH_CTRL_DSTINC_MASK         (0x400000UL)              /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_CTRL_BURST_SIZE_SHIFT    (24UL)                    /*!< BURST_SIZE (Bit 24)                                   */
#define DMA_DMA_CH_CTRL_BURST_SIZE_MASK     (0x1f000000UL)            /*!< BURST_SIZE (Bitfield-Mask: 0x1f)                      */
#define DMA_DMA_CH_CTRL_DIS_IE_SHIFT        (30UL)                    /*!< DIS_IE (Bit 30)                                       */
#define DMA_DMA_CH_CTRL_DIS_IE_MASK         (0x40000000UL)            /*!< DIS_IE (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_CTRL_CTZ_IE_SHIFT        (31UL)                    /*!< CTZ_IE (Bit 31)                                       */
#define DMA_DMA_CH_CTRL_CTZ_IE_MASK         (0x80000000UL)            /*!< CTZ_IE (Bitfield-Mask: 0x01)                          */
/* ========================================================  STATUS  ========================================================= */
#define DMA_DMA_CH_STATUS_STATUS_SHIFT      (0UL)                     /*!< STATUS (Bit 0)                                        */
#define DMA_DMA_CH_STATUS_STATUS_MASK       (0x1UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_STATUS_IPEND_SHIFT       (1UL)                     /*!< IPEND (Bit 1)                                         */
#define DMA_DMA_CH_STATUS_IPEND_MASK        (0x2UL)                   /*!< IPEND (Bitfield-Mask: 0x01)                           */
#define DMA_DMA_CH_STATUS_CTZ_IF_SHIFT      (2UL)                     /*!< CTZ_IF (Bit 2)                                        */
#define DMA_DMA_CH_STATUS_CTZ_IF_MASK       (0x4UL)                   /*!< CTZ_IF (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_STATUS_RLD_IF_SHIFT      (3UL)                     /*!< RLD_IF (Bit 3)                                        */
#define DMA_DMA_CH_STATUS_RLD_IF_MASK       (0x8UL)                   /*!< RLD_IF (Bitfield-Mask: 0x01)                          */
#define DMA_DMA_CH_STATUS_BUS_ERR_SHIFT     (4UL)                     /*!< BUS_ERR (Bit 4)                                       */
#define DMA_DMA_CH_STATUS_BUS_ERR_MASK      (0x10UL)                  /*!< BUS_ERR (Bitfield-Mask: 0x01)                         */
#define DMA_DMA_CH_STATUS_TO_IF_SHIFT       (6UL)                     /*!< TO_IF (Bit 6)                                         */
#define DMA_DMA_CH_STATUS_TO_IF_MASK        (0x40UL)                  /*!< TO_IF (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SRC  ========================================================== */
#define DMA_DMA_CH_SRC_ADDR_SHIFT           (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_DMA_CH_SRC_ADDR_MASK            (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  DST  ========================================================== */
#define DMA_DMA_CH_DST_ADDR_SHIFT           (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_DMA_CH_DST_ADDR_MASK            (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  CNT  ========================================================== */
#define DMA_DMA_CH_CNT_CNT_SHIFT            (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_DMA_CH_CNT_CNT_MASK             (0xffffffUL)              /*!< CNT (Bitfield-Mask: 0xffffff)                         */
/* ========================================================  SRCRLD  ========================================================= */
#define DMA_DMA_CH_SRCRLD_ADDR_SHIFT        (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_DMA_CH_SRCRLD_ADDR_MASK         (0x7fffffffUL)            /*!< ADDR (Bitfield-Mask: 0x7fffffff)                      */
/* ========================================================  DSTRLD  ========================================================= */
#define DMA_DMA_CH_DSTRLD_ADDR_SHIFT        (0UL)                     /*!< ADDR (Bit 0)                                          */
#define DMA_DMA_CH_DSTRLD_ADDR_MASK         (0x7fffffffUL)            /*!< ADDR (Bitfield-Mask: 0x7fffffff)                      */
/* ========================================================  CNTRLD  ========================================================= */
#define DMA_DMA_CH_CNTRLD_CNT_SHIFT         (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_DMA_CH_CNTRLD_CNT_MASK          (0xffffffUL)              /*!< CNT (Bitfield-Mask: 0xffffff)                         */
#define DMA_DMA_CH_CNTRLD_EN_SHIFT          (31UL)                    /*!< EN (Bit 31)                                           */
#define DMA_DMA_CH_CNTRLD_EN_MASK           (0x80000000UL)            /*!< EN (Bitfield-Mask: 0x01)                              */

/** @} */ /* End of group PosMask_clusters */


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define ADC_CTRL_START_SHIFT                (0UL)                     /*!< start (Bit 0)                                         */
#define ADC_CTRL_START_MASK                 (0x1UL)                   /*!< start (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL_PWR_SHIFT                  (1UL)                     /*!< pwr (Bit 1)                                           */
#define ADC_CTRL_PWR_MASK                   (0x2UL)                   /*!< pwr (Bitfield-Mask: 0x01)                             */
#define ADC_CTRL_REFBUF_PWR_SHIFT           (3UL)                     /*!< refbuf_pwr (Bit 3)                                    */
#define ADC_CTRL_REFBUF_PWR_MASK            (0x8UL)                   /*!< refbuf_pwr (Bitfield-Mask: 0x01)                      */
#define ADC_CTRL_REF_SEL_SHIFT              (4UL)                     /*!< ref_sel (Bit 4)                                       */
#define ADC_CTRL_REF_SEL_MASK               (0x10UL)                  /*!< ref_sel (Bitfield-Mask: 0x01)                         */
#define ADC_CTRL_REF_SCALE_SHIFT            (8UL)                     /*!< ref_scale (Bit 8)                                     */
#define ADC_CTRL_REF_SCALE_MASK             (0x100UL)                 /*!< ref_scale (Bitfield-Mask: 0x01)                       */
#define ADC_CTRL_SCALE_SHIFT                (9UL)                     /*!< scale (Bit 9)                                         */
#define ADC_CTRL_SCALE_MASK                 (0x200UL)                 /*!< scale (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL_CLK_EN_SHIFT               (11UL)                    /*!< clk_en (Bit 11)                                       */
#define ADC_CTRL_CLK_EN_MASK                (0x800UL)                 /*!< clk_en (Bitfield-Mask: 0x01)                          */
#define ADC_CTRL_CH_SEL_SHIFT               (12UL)                    /*!< ch_sel (Bit 12)                                       */
#define ADC_CTRL_CH_SEL_MASK                (0x1f000UL)               /*!< ch_sel (Bitfield-Mask: 0x1f)                          */
#define ADC_CTRL_ADC_DIVSEL_SHIFT           (17UL)                    /*!< adc_divsel (Bit 17)                                   */
#define ADC_CTRL_ADC_DIVSEL_MASK            (0x60000UL)               /*!< adc_divsel (Bitfield-Mask: 0x03)                      */
#define ADC_CTRL_DATA_ALIGN_SHIFT           (20UL)                    /*!< data_align (Bit 20)                                   */
#define ADC_CTRL_DATA_ALIGN_MASK            (0x100000UL)              /*!< data_align (Bitfield-Mask: 0x01)                      */
/* ========================================================  STATUS  ========================================================= */
#define ADC_STATUS_ACTIVE_SHIFT             (0UL)                     /*!< active (Bit 0)                                        */
#define ADC_STATUS_ACTIVE_MASK              (0x1UL)                   /*!< active (Bitfield-Mask: 0x01)                          */
#define ADC_STATUS_AFE_PWR_UP_ACTIVE_SHIFT  (2UL)                     /*!< afe_pwr_up_active (Bit 2)                             */
#define ADC_STATUS_AFE_PWR_UP_ACTIVE_MASK   (0x4UL)                   /*!< afe_pwr_up_active (Bitfield-Mask: 0x01)               */
#define ADC_STATUS_OVERFLOW_SHIFT           (3UL)                     /*!< overflow (Bit 3)                                      */
#define ADC_STATUS_OVERFLOW_MASK            (0x8UL)                   /*!< overflow (Bitfield-Mask: 0x01)                        */
/* =========================================================  DATA  ========================================================== */
#define ADC_DATA_ADC_DATA_SHIFT             (0UL)                     /*!< adc_data (Bit 0)                                      */
#define ADC_DATA_ADC_DATA_MASK              (0xffffUL)                /*!< adc_data (Bitfield-Mask: 0xffff)                      */
/* =========================================================  INTR  ========================================================== */
#define ADC_INTR_DONE_IE_SHIFT              (0UL)                     /*!< done_ie (Bit 0)                                       */
#define ADC_INTR_DONE_IE_MASK               (0x1UL)                   /*!< done_ie (Bitfield-Mask: 0x01)                         */
#define ADC_INTR_REF_READY_IE_SHIFT         (1UL)                     /*!< ref_ready_ie (Bit 1)                                  */
#define ADC_INTR_REF_READY_IE_MASK          (0x2UL)                   /*!< ref_ready_ie (Bitfield-Mask: 0x01)                    */
#define ADC_INTR_HI_LIMIT_IE_SHIFT          (2UL)                     /*!< hi_limit_ie (Bit 2)                                   */
#define ADC_INTR_HI_LIMIT_IE_MASK           (0x4UL)                   /*!< hi_limit_ie (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_LO_LIMIT_IE_SHIFT          (3UL)                     /*!< lo_limit_ie (Bit 3)                                   */
#define ADC_INTR_LO_LIMIT_IE_MASK           (0x8UL)                   /*!< lo_limit_ie (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_OVERFLOW_IE_SHIFT          (4UL)                     /*!< overflow_ie (Bit 4)                                   */
#define ADC_INTR_OVERFLOW_IE_MASK           (0x10UL)                  /*!< overflow_ie (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_DONE_IF_SHIFT              (16UL)                    /*!< done_if (Bit 16)                                      */
#define ADC_INTR_DONE_IF_MASK               (0x10000UL)               /*!< done_if (Bitfield-Mask: 0x01)                         */
#define ADC_INTR_REF_READY_IF_SHIFT         (17UL)                    /*!< ref_ready_if (Bit 17)                                 */
#define ADC_INTR_REF_READY_IF_MASK          (0x20000UL)               /*!< ref_ready_if (Bitfield-Mask: 0x01)                    */
#define ADC_INTR_HI_LIMIT_IF_SHIFT          (18UL)                    /*!< hi_limit_if (Bit 18)                                  */
#define ADC_INTR_HI_LIMIT_IF_MASK           (0x40000UL)               /*!< hi_limit_if (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_LO_LIMIT_IF_SHIFT          (19UL)                    /*!< lo_limit_if (Bit 19)                                  */
#define ADC_INTR_LO_LIMIT_IF_MASK           (0x80000UL)               /*!< lo_limit_if (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_OVERFLOW_IF_SHIFT          (20UL)                    /*!< overflow_if (Bit 20)                                  */
#define ADC_INTR_OVERFLOW_IF_MASK           (0x100000UL)              /*!< overflow_if (Bitfield-Mask: 0x01)                     */
#define ADC_INTR_PENDING_SHIFT              (22UL)                    /*!< pending (Bit 22)                                      */
#define ADC_INTR_PENDING_MASK               (0x400000UL)              /*!< pending (Bitfield-Mask: 0x01)                         */
/* =========================================================  LIMIT  ========================================================= */
#define ADC_LIMIT_CH_LO_LIMIT_SHIFT         (0UL)                     /*!< ch_lo_limit (Bit 0)                                   */
#define ADC_LIMIT_CH_LO_LIMIT_MASK          (0x3ffUL)                 /*!< ch_lo_limit (Bitfield-Mask: 0x3ff)                    */
#define ADC_LIMIT_CH_HI_LIMIT_SHIFT         (12UL)                    /*!< ch_hi_limit (Bit 12)                                  */
#define ADC_LIMIT_CH_HI_LIMIT_MASK          (0x3ff000UL)              /*!< ch_hi_limit (Bitfield-Mask: 0x3ff)                    */
#define ADC_LIMIT_CH_SEL_SHIFT              (24UL)                    /*!< ch_sel (Bit 24)                                       */
#define ADC_LIMIT_CH_SEL_MASK               (0x1f000000UL)            /*!< ch_sel (Bitfield-Mask: 0x1f)                          */
#define ADC_LIMIT_CH_LO_LIMIT_EN_SHIFT      (29UL)                    /*!< ch_lo_limit_en (Bit 29)                               */
#define ADC_LIMIT_CH_LO_LIMIT_EN_MASK       (0x20000000UL)            /*!< ch_lo_limit_en (Bitfield-Mask: 0x01)                  */
#define ADC_LIMIT_CH_HI_LIMIT_EN_SHIFT      (30UL)                    /*!< ch_hi_limit_en (Bit 30)                               */
#define ADC_LIMIT_CH_HI_LIMIT_EN_MASK       (0x40000000UL)            /*!< ch_hi_limit_en (Bitfield-Mask: 0x01)                  */


/* =========================================================================================================================== */
/* ================                                            AES                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define AES_CTRL_EN_SHIFT                   (0UL)                     /*!< EN (Bit 0)                                            */
#define AES_CTRL_EN_MASK                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define AES_CTRL_DMA_RX_EN_SHIFT            (1UL)                     /*!< DMA_RX_EN (Bit 1)                                     */
#define AES_CTRL_DMA_RX_EN_MASK             (0x2UL)                   /*!< DMA_RX_EN (Bitfield-Mask: 0x01)                       */
#define AES_CTRL_DMA_TX_EN_SHIFT            (2UL)                     /*!< DMA_TX_EN (Bit 2)                                     */
#define AES_CTRL_DMA_TX_EN_MASK             (0x4UL)                   /*!< DMA_TX_EN (Bitfield-Mask: 0x01)                       */
#define AES_CTRL_START_SHIFT                (3UL)                     /*!< START (Bit 3)                                         */
#define AES_CTRL_START_MASK                 (0x8UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
#define AES_CTRL_INPUT_FLUSH_SHIFT          (4UL)                     /*!< INPUT_FLUSH (Bit 4)                                   */
#define AES_CTRL_INPUT_FLUSH_MASK           (0x10UL)                  /*!< INPUT_FLUSH (Bitfield-Mask: 0x01)                     */
#define AES_CTRL_OUTPUT_FLUSH_SHIFT         (5UL)                     /*!< OUTPUT_FLUSH (Bit 5)                                  */
#define AES_CTRL_OUTPUT_FLUSH_MASK          (0x20UL)                  /*!< OUTPUT_FLUSH (Bitfield-Mask: 0x01)                    */
#define AES_CTRL_KEY_SIZE_SHIFT             (6UL)                     /*!< KEY_SIZE (Bit 6)                                      */
#define AES_CTRL_KEY_SIZE_MASK              (0xc0UL)                  /*!< KEY_SIZE (Bitfield-Mask: 0x03)                        */
#define AES_CTRL_TYPE_SHIFT                 (8UL)                     /*!< TYPE (Bit 8)                                          */
#define AES_CTRL_TYPE_MASK                  (0x300UL)                 /*!< TYPE (Bitfield-Mask: 0x03)                            */
/* ========================================================  STATUS  ========================================================= */
#define AES_STATUS_BUSY_SHIFT               (0UL)                     /*!< BUSY (Bit 0)                                          */
#define AES_STATUS_BUSY_MASK                (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define AES_STATUS_INPUT_EM_SHIFT           (1UL)                     /*!< INPUT_EM (Bit 1)                                      */
#define AES_STATUS_INPUT_EM_MASK            (0x2UL)                   /*!< INPUT_EM (Bitfield-Mask: 0x01)                        */
#define AES_STATUS_INPUT_FULL_SHIFT         (2UL)                     /*!< INPUT_FULL (Bit 2)                                    */
#define AES_STATUS_INPUT_FULL_MASK          (0x4UL)                   /*!< INPUT_FULL (Bitfield-Mask: 0x01)                      */
#define AES_STATUS_OUTPUT_EM_SHIFT          (3UL)                     /*!< OUTPUT_EM (Bit 3)                                     */
#define AES_STATUS_OUTPUT_EM_MASK           (0x8UL)                   /*!< OUTPUT_EM (Bitfield-Mask: 0x01)                       */
#define AES_STATUS_OUTPUT_FULL_SHIFT        (4UL)                     /*!< OUTPUT_FULL (Bit 4)                                   */
#define AES_STATUS_OUTPUT_FULL_MASK         (0x10UL)                  /*!< OUTPUT_FULL (Bitfield-Mask: 0x01)                     */
/* =========================================================  INTFL  ========================================================= */
#define AES_INTFL_DONE_SHIFT                (0UL)                     /*!< DONE (Bit 0)                                          */
#define AES_INTFL_DONE_MASK                 (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define AES_INTFL_KEY_CHANGE_SHIFT          (1UL)                     /*!< KEY_CHANGE (Bit 1)                                    */
#define AES_INTFL_KEY_CHANGE_MASK           (0x2UL)                   /*!< KEY_CHANGE (Bitfield-Mask: 0x01)                      */
#define AES_INTFL_KEY_ZERO_SHIFT            (2UL)                     /*!< KEY_ZERO (Bit 2)                                      */
#define AES_INTFL_KEY_ZERO_MASK             (0x4UL)                   /*!< KEY_ZERO (Bitfield-Mask: 0x01)                        */
#define AES_INTFL_OV_SHIFT                  (3UL)                     /*!< OV (Bit 3)                                            */
#define AES_INTFL_OV_MASK                   (0x8UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
#define AES_INTFL_KEY_ONE_SHIFT             (4UL)                     /*!< KEY_ONE (Bit 4)                                       */
#define AES_INTFL_KEY_ONE_MASK              (0x10UL)                  /*!< KEY_ONE (Bitfield-Mask: 0x01)                         */
/* =========================================================  INTEN  ========================================================= */
#define AES_INTEN_DONE_SHIFT                (0UL)                     /*!< DONE (Bit 0)                                          */
#define AES_INTEN_DONE_MASK                 (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define AES_INTEN_KEY_CHANGE_SHIFT          (1UL)                     /*!< KEY_CHANGE (Bit 1)                                    */
#define AES_INTEN_KEY_CHANGE_MASK           (0x2UL)                   /*!< KEY_CHANGE (Bitfield-Mask: 0x01)                      */
#define AES_INTEN_KEY_ZERO_SHIFT            (2UL)                     /*!< KEY_ZERO (Bit 2)                                      */
#define AES_INTEN_KEY_ZERO_MASK             (0x4UL)                   /*!< KEY_ZERO (Bitfield-Mask: 0x01)                        */
#define AES_INTEN_OV_SHIFT                  (3UL)                     /*!< OV (Bit 3)                                            */
#define AES_INTEN_OV_MASK                   (0x8UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
#define AES_INTEN_KEY_ONE_SHIFT             (4UL)                     /*!< KEY_ONE (Bit 4)                                       */
#define AES_INTEN_KEY_ONE_MASK              (0x10UL)                  /*!< KEY_ONE (Bitfield-Mask: 0x01)                         */
/* =========================================================  FIFO  ========================================================== */
#define AES_FIFO_DATA_SHIFT                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define AES_FIFO_DATA_MASK                  (0x1UL)                   /*!< DATA (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                          AES_KEY                                          ================ */
/* =========================================================================================================================== */

/* =======================================================  AES_KEY0  ======================================================== */
/* =======================================================  AES_KEY1  ======================================================== */
/* =======================================================  AES_KEY2  ======================================================== */
/* =======================================================  AES_KEY3  ======================================================== */
/* =======================================================  AES_KEY4  ======================================================== */
/* =======================================================  AES_KEY5  ======================================================== */
/* =======================================================  AES_KEY6  ======================================================== */
/* =======================================================  AES_KEY7  ======================================================== */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define CRC_CTRL_EN_SHIFT                   (0UL)                     /*!< EN (Bit 0)                                            */
#define CRC_CTRL_EN_MASK                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define CRC_CTRL_DMA_EN_SHIFT               (1UL)                     /*!< DMA_EN (Bit 1)                                        */
#define CRC_CTRL_DMA_EN_MASK                (0x2UL)                   /*!< DMA_EN (Bitfield-Mask: 0x01)                          */
#define CRC_CTRL_MSB_SHIFT                  (2UL)                     /*!< MSB (Bit 2)                                           */
#define CRC_CTRL_MSB_MASK                   (0x4UL)                   /*!< MSB (Bitfield-Mask: 0x01)                             */
#define CRC_CTRL_BYTE_SWAP_IN_SHIFT         (3UL)                     /*!< BYTE_SWAP_IN (Bit 3)                                  */
#define CRC_CTRL_BYTE_SWAP_IN_MASK          (0x8UL)                   /*!< BYTE_SWAP_IN (Bitfield-Mask: 0x01)                    */
#define CRC_CTRL_BYTE_SWAP_OUT_SHIFT        (4UL)                     /*!< BYTE_SWAP_OUT (Bit 4)                                 */
#define CRC_CTRL_BYTE_SWAP_OUT_MASK         (0x10UL)                  /*!< BYTE_SWAP_OUT (Bitfield-Mask: 0x01)                   */
#define CRC_CTRL_BUSY_SHIFT                 (16UL)                    /*!< BUSY (Bit 16)                                         */
#define CRC_CTRL_BUSY_MASK                  (0x10000UL)               /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* =======================================================  DATAIN32  ======================================================== */
#define CRC_DATAIN32_DATA_SHIFT             (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATAIN32_DATA_MASK              (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  DATAIN16  ======================================================== */
#define CRC_DATAIN16_DATA_SHIFT             (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATAIN16_DATA_MASK              (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* ========================================================  DATAIN8  ======================================================== */
#define CRC_DATAIN8_DATA_SHIFT              (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATAIN8_DATA_MASK               (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  POLY  ========================================================== */
#define CRC_POLY_POLY_SHIFT                 (0UL)                     /*!< POLY (Bit 0)                                          */
#define CRC_POLY_POLY_MASK                  (0xffffffffUL)            /*!< POLY (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  VAL  ========================================================== */
#define CRC_VAL_VALUE_SHIFT                 (0UL)                     /*!< VALUE (Bit 0)                                         */
#define CRC_VAL_VALUE_MASK                  (0xffffffffUL)            /*!< VALUE (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INTEN  ========================================================= */
#define DMA_INTEN_CH0_SHIFT                 (0UL)                     /*!< CH0 (Bit 0)                                           */
#define DMA_INTEN_CH0_MASK                  (0x1UL)                   /*!< CH0 (Bitfield-Mask: 0x01)                             */
#define DMA_INTEN_CH1_SHIFT                 (1UL)                     /*!< CH1 (Bit 1)                                           */
#define DMA_INTEN_CH1_MASK                  (0x2UL)                   /*!< CH1 (Bitfield-Mask: 0x01)                             */
#define DMA_INTEN_CH2_SHIFT                 (2UL)                     /*!< CH2 (Bit 2)                                           */
#define DMA_INTEN_CH2_MASK                  (0x4UL)                   /*!< CH2 (Bitfield-Mask: 0x01)                             */
#define DMA_INTEN_CH3_SHIFT                 (3UL)                     /*!< CH3 (Bit 3)                                           */
#define DMA_INTEN_CH3_MASK                  (0x8UL)                   /*!< CH3 (Bitfield-Mask: 0x01)                             */
/* =========================================================  INTFL  ========================================================= */
#define DMA_INTFL_CH0_SHIFT                 (0UL)                     /*!< CH0 (Bit 0)                                           */
#define DMA_INTFL_CH0_MASK                  (0x1UL)                   /*!< CH0 (Bitfield-Mask: 0x01)                             */
#define DMA_INTFL_CH1_SHIFT                 (1UL)                     /*!< CH1 (Bit 1)                                           */
#define DMA_INTFL_CH1_MASK                  (0x2UL)                   /*!< CH1 (Bitfield-Mask: 0x01)                             */
#define DMA_INTFL_CH2_SHIFT                 (2UL)                     /*!< CH2 (Bit 2)                                           */
#define DMA_INTFL_CH2_MASK                  (0x4UL)                   /*!< CH2 (Bitfield-Mask: 0x01)                             */
#define DMA_INTFL_CH3_SHIFT                 (3UL)                     /*!< CH3 (Bit 3)                                           */
#define DMA_INTFL_CH3_MASK                  (0x8UL)                   /*!< CH3 (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            FLC                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  FLSH_ADDR  ======================================================= */
#define FLC_ADDR_ADDR_SHIFT                 (0UL)                     /*!< ADDR (Bit 0)                                          */
#define FLC_ADDR_ADDR_MASK                  (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  FLSH_CLKDIV  ====================================================== */
#define FLC_CLKDIV_CLKDIV_SHIFT             (0UL)                     /*!< CLKDIV (Bit 0)                                        */
#define FLC_CLKDIV_CLKDIV_MASK              (0xffUL)                  /*!< CLKDIV (Bitfield-Mask: 0xff)                          */
/* =======================================================  FLSH_CTRL  ======================================================= */
#define FLC_CTRL_WR_SHIFT                   (0UL)                     /*!< WR (Bit 0)                                            */
#define FLC_CTRL_WR_MASK                    (0x1UL)                   /*!< WR (Bitfield-Mask: 0x01)                              */
#define FLC_CTRL_ME_SHIFT                   (1UL)                     /*!< ME (Bit 1)                                            */
#define FLC_CTRL_ME_MASK                    (0x2UL)                   /*!< ME (Bitfield-Mask: 0x01)                              */
#define FLC_CTRL_PGE_SHIFT                  (2UL)                     /*!< PGE (Bit 2)                                           */
#define FLC_CTRL_PGE_MASK                   (0x4UL)                   /*!< PGE (Bitfield-Mask: 0x01)                             */
#define FLC_CTRL_WDTH_SHIFT                 (4UL)                     /*!< WDTH (Bit 4)                                          */
#define FLC_CTRL_WDTH_MASK                  (0x10UL)                  /*!< WDTH (Bitfield-Mask: 0x01)                            */
#define FLC_CTRL_ERASE_CODE_SHIFT           (8UL)                     /*!< ERASE_CODE (Bit 8)                                    */
#define FLC_CTRL_ERASE_CODE_MASK            (0xff00UL)                /*!< ERASE_CODE (Bitfield-Mask: 0xff)                      */
#define FLC_CTRL_PEND_SHIFT                 (24UL)                    /*!< PEND (Bit 24)                                         */
#define FLC_CTRL_PEND_MASK                  (0x1000000UL)             /*!< PEND (Bitfield-Mask: 0x01)                            */
#define FLC_CTRL_LVE_SHIFT                  (25UL)                    /*!< LVE (Bit 25)                                          */
#define FLC_CTRL_LVE_MASK                   (0x2000000UL)             /*!< LVE (Bitfield-Mask: 0x01)                             */
#define FLC_CTRL_UNLOCK_SHIFT               (28UL)                    /*!< UNLOCK (Bit 28)                                       */
#define FLC_CTRL_UNLOCK_MASK                (0xf0000000UL)            /*!< UNLOCK (Bitfield-Mask: 0x0f)                          */
/* =======================================================  FLSH_INTR  ======================================================= */
#define FLC_INTR_DONE_SHIFT                 (0UL)                     /*!< DONE (Bit 0)                                          */
#define FLC_INTR_DONE_MASK                  (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define FLC_INTR_AF_SHIFT                   (1UL)                     /*!< AF (Bit 1)                                            */
#define FLC_INTR_AF_MASK                    (0x2UL)                   /*!< AF (Bitfield-Mask: 0x01)                              */
#define FLC_INTR_DONEIE_SHIFT               (8UL)                     /*!< DONEIE (Bit 8)                                        */
#define FLC_INTR_DONEIE_MASK                (0x100UL)                 /*!< DONEIE (Bitfield-Mask: 0x01)                          */
#define FLC_INTR_AFIE_SHIFT                 (9UL)                     /*!< AFIE (Bit 9)                                          */
#define FLC_INTR_AFIE_MASK                  (0x200UL)                 /*!< AFIE (Bitfield-Mask: 0x01)                            */
/* =====================================================  FLSH_ECCDATA  ====================================================== */
#define FLC_ECCDATA_EVEN_SHIFT              (0UL)                     /*!< EVEN (Bit 0)                                          */
#define FLC_ECCDATA_EVEN_MASK               (0x1ffUL)                 /*!< EVEN (Bitfield-Mask: 0x1ff)                           */
#define FLC_ECCDATA_ODD_SHIFT               (16UL)                    /*!< ODD (Bit 16)                                          */
#define FLC_ECCDATA_ODD_MASK                (0x1ff0000UL)             /*!< ODD (Bitfield-Mask: 0x1ff)                            */
/* ======================================================  FLSH_ACTRL  ======================================================= */
#define FLC_ACTRL_ACTRL_SHIFT               (0UL)                     /*!< ACTRL (Bit 0)                                         */
#define FLC_ACTRL_ACTRL_MASK                (0xffffffffUL)            /*!< ACTRL (Bitfield-Mask: 0xffffffff)                     */
/* ======================================================  FLSH_WELR0  ======================================================= */
#define FLC_WELR0_WELR0_SHIFT               (0UL)                     /*!< WELR0 (Bit 0)                                         */
#define FLC_WELR0_WELR0_MASK                (0xffffffffUL)            /*!< WELR0 (Bitfield-Mask: 0xffffffff)                     */
/* ======================================================  FLSH_WELR1  ======================================================= */
#define FLC_WELR1_WELR1_SHIFT               (0UL)                     /*!< WELR1 (Bit 0)                                         */
#define FLC_WELR1_WELR1_MASK                (0xffffffffUL)            /*!< WELR1 (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  FLSH_RLR0  ======================================================= */
#define FLC_RLR0_RLR0_SHIFT                 (0UL)                     /*!< RLR0 (Bit 0)                                          */
#define FLC_RLR0_RLR0_MASK                  (0xffffffffUL)            /*!< RLR0 (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  FLSH_RLR1  ======================================================= */
#define FLC_RLR1_RLR1_SHIFT                 (0UL)                     /*!< RLR1 (Bit 0)                                          */
#define FLC_RLR1_RLR1_MASK                  (0xffffffffUL)            /*!< RLR1 (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                            GCR                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  SYSCTRL  ======================================================== */
#define GCR_SYSCTRL_BSTAPEN_SHIFT           (1UL)                     /*!< BSTAPEN (Bit 1)                                       */
#define GCR_SYSCTRL_BSTAPEN_MASK            (0x2UL)                   /*!< BSTAPEN (Bitfield-Mask: 0x01)                         */
#define GCR_SYSCTRL_FLASH_PAGE_FLIP_SHIFT   (4UL)                     /*!< FLASH_PAGE_FLIP (Bit 4)                               */
#define GCR_SYSCTRL_FLASH_PAGE_FLIP_MASK    (0x10UL)                  /*!< FLASH_PAGE_FLIP (Bitfield-Mask: 0x01)                 */
#define GCR_SYSCTRL_ICC0_FLUSH_SHIFT        (6UL)                     /*!< ICC0_FLUSH (Bit 6)                                    */
#define GCR_SYSCTRL_ICC0_FLUSH_MASK         (0x40UL)                  /*!< ICC0_FLUSH (Bitfield-Mask: 0x01)                      */
#define GCR_SYSCTRL_ROMDONE_SHIFT           (12UL)                    /*!< ROMDONE (Bit 12)                                      */
#define GCR_SYSCTRL_ROMDONE_MASK            (0x1000UL)                /*!< ROMDONE (Bitfield-Mask: 0x01)                         */
#define GCR_SYSCTRL_CCHK_SHIFT              (13UL)                    /*!< CCHK (Bit 13)                                         */
#define GCR_SYSCTRL_CCHK_MASK               (0x2000UL)                /*!< CCHK (Bitfield-Mask: 0x01)                            */
#define GCR_SYSCTRL_SWD_DIS_SHIFT           (14UL)                    /*!< SWD_DIS (Bit 14)                                      */
#define GCR_SYSCTRL_SWD_DIS_MASK            (0x4000UL)                /*!< SWD_DIS (Bitfield-Mask: 0x01)                         */
#define GCR_SYSCTRL_CHKRES_SHIFT            (15UL)                    /*!< CHKRES (Bit 15)                                       */
#define GCR_SYSCTRL_CHKRES_MASK             (0x8000UL)                /*!< CHKRES (Bitfield-Mask: 0x01)                          */
#define GCR_SYSCTRL_OVR_SHIFT               (16UL)                    /*!< OVR (Bit 16)                                          */
#define GCR_SYSCTRL_OVR_MASK                (0x30000UL)               /*!< OVR (Bitfield-Mask: 0x03)                             */
/* =========================================================  RST0  ========================================================== */
#define GCR_RST0_DMA_SHIFT                  (0UL)                     /*!< DMA (Bit 0)                                           */
#define GCR_RST0_DMA_MASK                   (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
#define GCR_RST0_WDT0_SHIFT                 (1UL)                     /*!< WDT0 (Bit 1)                                          */
#define GCR_RST0_WDT0_MASK                  (0x2UL)                   /*!< WDT0 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_GPIO0_SHIFT                (2UL)                     /*!< GPIO0 (Bit 2)                                         */
#define GCR_RST0_GPIO0_MASK                 (0x4UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_GPIO1_SHIFT                (3UL)                     /*!< GPIO1 (Bit 3)                                         */
#define GCR_RST0_GPIO1_MASK                 (0x8UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_TMR0_SHIFT                 (5UL)                     /*!< TMR0 (Bit 5)                                          */
#define GCR_RST0_TMR0_MASK                  (0x20UL)                  /*!< TMR0 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_TMR1_SHIFT                 (6UL)                     /*!< TMR1 (Bit 6)                                          */
#define GCR_RST0_TMR1_MASK                  (0x40UL)                  /*!< TMR1 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_TMR2_SHIFT                 (7UL)                     /*!< TMR2 (Bit 7)                                          */
#define GCR_RST0_TMR2_MASK                  (0x80UL)                  /*!< TMR2 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_TMR3_SHIFT                 (8UL)                     /*!< TMR3 (Bit 8)                                          */
#define GCR_RST0_TMR3_MASK                  (0x100UL)                 /*!< TMR3 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_UART0_SHIFT                (11UL)                    /*!< UART0 (Bit 11)                                        */
#define GCR_RST0_UART0_MASK                 (0x800UL)                 /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_UART1_SHIFT                (12UL)                    /*!< UART1 (Bit 12)                                        */
#define GCR_RST0_UART1_MASK                 (0x1000UL)                /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_SPI1_SHIFT                 (13UL)                    /*!< SPI1 (Bit 13)                                         */
#define GCR_RST0_SPI1_MASK                  (0x2000UL)                /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_I2C_SHIFT                 (16UL)                    /*!< I2C0 (Bit 16)                                         */
#define GCR_RST0_I2C_MASK                  (0x10000UL)               /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_RTC_SHIFT                  (17UL)                    /*!< RTC (Bit 17)                                          */
#define GCR_RST0_RTC_MASK                   (0x20000UL)               /*!< RTC (Bitfield-Mask: 0x01)                             */
#define GCR_RST0_SMPHR_SHIFT                (22UL)                    /*!< SMPHR (Bit 22)                                        */
#define GCR_RST0_SMPHR_MASK                 (0x400000UL)              /*!< SMPHR (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_TRNG_SHIFT                 (24UL)                    /*!< TRNG (Bit 24)                                         */
#define GCR_RST0_TRNG_MASK                  (0x1000000UL)             /*!< TRNG (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_CNN_SHIFT                  (25UL)                    /*!< CNN (Bit 25)                                          */
#define GCR_RST0_CNN_MASK                   (0x2000000UL)             /*!< CNN (Bitfield-Mask: 0x01)                             */
#define GCR_RST0_ADC_SHIFT                  (26UL)                    /*!< ADC (Bit 26)                                          */
#define GCR_RST0_ADC_MASK                   (0x4000000UL)             /*!< ADC (Bitfield-Mask: 0x01)                             */
#define GCR_RST0_UART2_SHIFT                (28UL)                    /*!< UART2 (Bit 28)                                        */
#define GCR_RST0_UART2_MASK                 (0x10000000UL)            /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define GCR_RST0_SOFT_SHIFT                 (29UL)                    /*!< SOFT (Bit 29)                                         */
#define GCR_RST0_SOFT_MASK                  (0x20000000UL)            /*!< SOFT (Bitfield-Mask: 0x01)                            */
#define GCR_RST0_PERIPH_SHIFT               (30UL)                    /*!< PERIPH (Bit 30)                                       */
#define GCR_RST0_PERIPH_MASK                (0x40000000UL)            /*!< PERIPH (Bitfield-Mask: 0x01)                          */
#define GCR_RST0_SYS_SHIFT                  (31UL)                    /*!< SYS (Bit 31)                                          */
#define GCR_RST0_SYS_MASK                   (0x80000000UL)            /*!< SYS (Bitfield-Mask: 0x01)                             */
/* ========================================================  CLKCTRL  ======================================================== */
#define GCR_CLKCTRL_SYSCLK_DIV_SHIFT        (6UL)                     /*!< SYSCLK_DIV (Bit 6)                                    */
#define GCR_CLKCTRL_SYSCLK_DIV_MASK         (0x1c0UL)                 /*!< SYSCLK_DIV (Bitfield-Mask: 0x07)                      */
#define GCR_CLKCTRL_SYSCLK_SEL_SHIFT        (9UL)                     /*!< SYSCLK_SEL (Bit 9)                                    */
#define GCR_CLKCTRL_SYSCLK_SEL_MASK         (0xe00UL)                 /*!< SYSCLK_SEL (Bitfield-Mask: 0x07)                      */
#define GCR_CLKCTRL_SYSCLK_RDY_SHIFT        (13UL)                    /*!< SYSCLK_RDY (Bit 13)                                   */
#define GCR_CLKCTRL_SYSCLK_RDY_MASK         (0x2000UL)                /*!< SYSCLK_RDY (Bitfield-Mask: 0x01)                      */
#define GCR_CLKCTRL_ERTCO_EN_SHIFT          (17UL)                    /*!< ERTCO_EN (Bit 17)                                     */
#define GCR_CLKCTRL_ERTCO_EN_MASK           (0x20000UL)               /*!< ERTCO_EN (Bitfield-Mask: 0x01)                        */
#define GCR_CLKCTRL_ISO_EN_SHIFT            (18UL)                    /*!< ISO_EN (Bit 18)                                       */
#define GCR_CLKCTRL_ISO_EN_MASK             (0x40000UL)               /*!< ISO_EN (Bitfield-Mask: 0x01)                          */
#define GCR_CLKCTRL_IPO_EN_SHIFT            (19UL)                    /*!< IPO_EN (Bit 19)                                       */
#define GCR_CLKCTRL_IPO_EN_MASK             (0x80000UL)               /*!< IPO_EN (Bitfield-Mask: 0x01)                          */
#define GCR_CLKCTRL_IBRO_EN_SHIFT           (20UL)                    /*!< IBRO_EN (Bit 20)                                      */
#define GCR_CLKCTRL_IBRO_EN_MASK            (0x100000UL)              /*!< IBRO_EN (Bitfield-Mask: 0x01)                         */
#define GCR_CLKCTRL_IBRO_VS_SHIFT           (21UL)                    /*!< IBRO_VS (Bit 21)                                      */
#define GCR_CLKCTRL_IBRO_VS_MASK            (0x200000UL)              /*!< IBRO_VS (Bitfield-Mask: 0x01)                         */
#define GCR_CLKCTRL_ERTCO_RDY_SHIFT         (25UL)                    /*!< ERTCO_RDY (Bit 25)                                    */
#define GCR_CLKCTRL_ERTCO_RDY_MASK          (0x2000000UL)             /*!< ERTCO_RDY (Bitfield-Mask: 0x01)                       */
#define GCR_CLKCTRL_ISO_RDY_SHIFT           (26UL)                    /*!< ISO_RDY (Bit 26)                                      */
#define GCR_CLKCTRL_ISO_RDY_MASK            (0x4000000UL)             /*!< ISO_RDY (Bitfield-Mask: 0x01)                         */
#define GCR_CLKCTRL_IPO_RDY_SHIFT           (27UL)                    /*!< IPO_RDY (Bit 27)                                      */
#define GCR_CLKCTRL_IPO_RDY_MASK            (0x8000000UL)             /*!< IPO_RDY (Bitfield-Mask: 0x01)                         */
#define GCR_CLKCTRL_IBRO_RDY_SHIFT          (28UL)                    /*!< IBRO_RDY (Bit 28)                                     */
#define GCR_CLKCTRL_IBRO_RDY_MASK           (0x10000000UL)            /*!< IBRO_RDY (Bitfield-Mask: 0x01)                        */
#define GCR_CLKCTRL_INRO_RDY_SHIFT          (29UL)                    /*!< INRO_RDY (Bit 29)                                     */
#define GCR_CLKCTRL_INRO_RDY_MASK           (0x20000000UL)            /*!< INRO_RDY (Bitfield-Mask: 0x01)                        */
/* ==========================================================  PM  =========================================================== */
#define GCR_PM_MODE_SHIFT                   (0UL)                     /*!< MODE (Bit 0)                                          */
#define GCR_PM_MODE_MASK                    (0xfUL)                   /*!< MODE (Bitfield-Mask: 0x0f)                            */
#define GCR_PM_GPIO_WE_SHIFT                (4UL)                     /*!< GPIO_WE (Bit 4)                                       */
#define GCR_PM_GPIO_WE_MASK                 (0x10UL)                  /*!< GPIO_WE (Bitfield-Mask: 0x01)                         */
#define GCR_PM_RTC_WE_SHIFT                 (5UL)                     /*!< RTC_WE (Bit 5)                                        */
#define GCR_PM_RTC_WE_MASK                  (0x20UL)                  /*!< RTC_WE (Bitfield-Mask: 0x01)                          */
#define GCR_PM_WUT_WE_SHIFT                 (7UL)                     /*!< WUT_WE (Bit 7)                                        */
#define GCR_PM_WUT_WE_MASK                  (0x80UL)                  /*!< WUT_WE (Bitfield-Mask: 0x01)                          */
#define GCR_PM_AINCOMP_WE_SHIFT             (9UL)                     /*!< AINCOMP_WE (Bit 9)                                    */
#define GCR_PM_AINCOMP_WE_MASK              (0x200UL)                 /*!< AINCOMP_WE (Bitfield-Mask: 0x01)                      */
#define GCR_PM_ISO_PD_SHIFT                 (15UL)                    /*!< ISO_PD (Bit 15)                                       */
#define GCR_PM_ISO_PD_MASK                  (0x8000UL)                /*!< ISO_PD (Bitfield-Mask: 0x01)                          */
#define GCR_PM_IPO_PD_SHIFT                 (16UL)                    /*!< IPO_PD (Bit 16)                                       */
#define GCR_PM_IPO_PD_MASK                  (0x10000UL)               /*!< IPO_PD (Bitfield-Mask: 0x01)                          */
#define GCR_PM_IBRO_PD_SHIFT                (17UL)                    /*!< IBRO_PD (Bit 17)                                      */
#define GCR_PM_IBRO_PD_MASK                 (0x20000UL)               /*!< IBRO_PD (Bitfield-Mask: 0x01)                         */
/* ========================================================  PCLKDIV  ======================================================== */
#define GCR_PCLKDIV_ADCFRQ_SHIFT            (10UL)                    /*!< ADCFRQ (Bit 10)                                       */
#define GCR_PCLKDIV_ADCFRQ_MASK             (0x1c00UL)                /*!< ADCFRQ (Bitfield-Mask: 0x07)                          */
#define GCR_PCLKDIV_CNNCLKDIV_SHIFT         (14UL)                    /*!< CNNCLKDIV (Bit 14)                                    */
#define GCR_PCLKDIV_CNNCLKDIV_MASK          (0x1c000UL)               /*!< CNNCLKDIV (Bitfield-Mask: 0x07)                       */
#define GCR_PCLKDIV_CNNCLKSEL_SHIFT         (17UL)                    /*!< CNNCLKSEL (Bit 17)                                    */
#define GCR_PCLKDIV_CNNCLKSEL_MASK          (0x20000UL)               /*!< CNNCLKSEL (Bitfield-Mask: 0x01)                       */
/* =======================================================  PCLKDIS0  ======================================================== */
#define GCR_PCLKDIS0_GPIO0_SHIFT            (0UL)                     /*!< GPIO0 (Bit 0)                                         */
#define GCR_PCLKDIS0_GPIO0_MASK             (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS0_GPIO1_SHIFT            (1UL)                     /*!< GPIO1 (Bit 1)                                         */
#define GCR_PCLKDIS0_GPIO1_MASK             (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS0_DMA_SHIFT              (5UL)                     /*!< DMA (Bit 5)                                           */
#define GCR_PCLKDIS0_DMA_MASK               (0x20UL)                  /*!< DMA (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS0_SPI1_SHIFT             (6UL)                     /*!< SPI1 (Bit 6)                                          */
#define GCR_PCLKDIS0_SPI1_MASK              (0x40UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_UART0_SHIFT            (9UL)                     /*!< UART0 (Bit 9)                                         */
#define GCR_PCLKDIS0_UART0_MASK             (0x200UL)                 /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS0_UART1_SHIFT            (10UL)                    /*!< UART1 (Bit 10)                                        */
#define GCR_PCLKDIS0_UART1_MASK             (0x400UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS0_I2C0_SHIFT             (13UL)                    /*!< I2C0 (Bit 13)                                         */
#define GCR_PCLKDIS0_I2C0_MASK              (0x2000UL)                /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_TMR0_SHIFT             (15UL)                    /*!< TMR0 (Bit 15)                                         */
#define GCR_PCLKDIS0_TMR0_MASK              (0x8000UL)                /*!< TMR0 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_TMR1_SHIFT             (16UL)                    /*!< TMR1 (Bit 16)                                         */
#define GCR_PCLKDIS0_TMR1_MASK              (0x10000UL)               /*!< TMR1 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_TMR2_SHIFT             (17UL)                    /*!< TMR2 (Bit 17)                                         */
#define GCR_PCLKDIS0_TMR2_MASK              (0x20000UL)               /*!< TMR2 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_TMR3_SHIFT             (18UL)                    /*!< TMR3 (Bit 18)                                         */
#define GCR_PCLKDIS0_TMR3_MASK              (0x40000UL)               /*!< TMR3 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_ADC_SHIFT              (23UL)                    /*!< ADC (Bit 23)                                          */
#define GCR_PCLKDIS0_ADC_MASK               (0x800000UL)              /*!< ADC (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS0_CNN_SHIFT              (25UL)                    /*!< CNN (Bit 25)                                          */
#define GCR_PCLKDIS0_CNN_MASK               (0x2000000UL)             /*!< CNN (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS0_I2C1_SHIFT             (28UL)                    /*!< I2C1 (Bit 28)                                         */
#define GCR_PCLKDIS0_I2C1_MASK              (0x10000000UL)            /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS0_PT_SHIFT               (29UL)                    /*!< PT (Bit 29)                                           */
#define GCR_PCLKDIS0_PT_MASK                (0x20000000UL)            /*!< PT (Bitfield-Mask: 0x01)                              */
/* ========================================================  MEMCTRL  ======================================================== */
#define GCR_MEMCTRL_FWS_SHIFT               (0UL)                     /*!< FWS (Bit 0)                                           */
#define GCR_MEMCTRL_FWS_MASK                (0x7UL)                   /*!< FWS (Bitfield-Mask: 0x07)                             */
#define GCR_MEMCTRL_SYSRAM0ECC_SHIFT        (16UL)                    /*!< SYSRAM0ECC (Bit 16)                                   */
#define GCR_MEMCTRL_SYSRAM0ECC_MASK         (0x10000UL)               /*!< SYSRAM0ECC (Bitfield-Mask: 0x01)                      */
/* =========================================================  MEMZ  ========================================================== */
#define GCR_MEMZ_RAM0_SHIFT                 (0UL)                     /*!< RAM0 (Bit 0)                                          */
#define GCR_MEMZ_RAM0_MASK                  (0x1UL)                   /*!< RAM0 (Bitfield-Mask: 0x01)                            */
#define GCR_MEMZ_RAM1_SHIFT                 (1UL)                     /*!< RAM1 (Bit 1)                                          */
#define GCR_MEMZ_RAM1_MASK                  (0x2UL)                   /*!< RAM1 (Bitfield-Mask: 0x01)                            */
#define GCR_MEMZ_RAM2_SHIFT                 (2UL)                     /*!< RAM2 (Bit 2)                                          */
#define GCR_MEMZ_RAM2_MASK                  (0x4UL)                   /*!< RAM2 (Bitfield-Mask: 0x01)                            */
#define GCR_MEMZ_RAM3_SHIFT                 (3UL)                     /*!< RAM3 (Bit 3)                                          */
#define GCR_MEMZ_RAM3_MASK                  (0x8UL)                   /*!< RAM3 (Bitfield-Mask: 0x01)                            */
#define GCR_MEMZ_SYSRAM0ECC_SHIFT           (4UL)                     /*!< SYSRAM0ECC (Bit 4)                                    */
#define GCR_MEMZ_SYSRAM0ECC_MASK            (0x10UL)                  /*!< SYSRAM0ECC (Bitfield-Mask: 0x01)                      */
#define GCR_MEMZ_ICC0_SHIFT                 (5UL)                     /*!< ICC0 (Bit 5)                                          */
#define GCR_MEMZ_ICC0_MASK                  (0x20UL)                  /*!< ICC0 (Bitfield-Mask: 0x01)                            */
#define GCR_MEMZ_ICC1_SHIFT                 (6UL)                     /*!< ICC1 (Bit 6)                                          */
#define GCR_MEMZ_ICC1_MASK                  (0x40UL)                  /*!< ICC1 (Bitfield-Mask: 0x01)                            */
/* =========================================================  SYSST  ========================================================= */
#define GCR_SYSST_ICELOCK_SHIFT             (0UL)                     /*!< ICELOCK (Bit 0)                                       */
#define GCR_SYSST_ICELOCK_MASK              (0x1UL)                   /*!< ICELOCK (Bitfield-Mask: 0x01)                         */
/* =========================================================  RST1  ========================================================== */
#define GCR_RST1_I2C1_SHIFT                 (0UL)                     /*!< I2C1 (Bit 0)                                          */
#define GCR_RST1_I2C1_MASK                  (0x1UL)                   /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define GCR_RST1_PT_SHIFT                   (1UL)                     /*!< PT (Bit 1)                                            */
#define GCR_RST1_PT_MASK                    (0x2UL)                   /*!< PT (Bitfield-Mask: 0x01)                              */
#define GCR_RST1_OWM_SHIFT                  (7UL)                     /*!< OWM (Bit 7)                                           */
#define GCR_RST1_OWM_MASK                   (0x80UL)                  /*!< OWM (Bitfield-Mask: 0x01)                             */
#define GCR_RST1_CRC_SHIFT                  (9UL)                     /*!< CRC (Bit 9)                                           */
#define GCR_RST1_CRC_MASK                   (0x200UL)                 /*!< CRC (Bitfield-Mask: 0x01)                             */
#define GCR_RST1_AES_SHIFT                  (10UL)                    /*!< AES (Bit 10)                                          */
#define GCR_RST1_AES_MASK                   (0x400UL)                 /*!< AES (Bitfield-Mask: 0x01)                             */
#define GCR_RST1_SPI0_SHIFT                 (11UL)                    /*!< SPI0 (Bit 11)                                         */
#define GCR_RST1_SPI0_MASK                  (0x800UL)                 /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define GCR_RST1_SMPHR_SHIFT                (16UL)                    /*!< SMPHR (Bit 16)                                        */
#define GCR_RST1_SMPHR_MASK                 (0x10000UL)               /*!< SMPHR (Bitfield-Mask: 0x01)                           */
#define GCR_RST1_I2S_SHIFT                  (19UL)                    /*!< I2S (Bit 19)                                          */
#define GCR_RST1_I2S_MASK                   (0x80000UL)               /*!< I2S (Bitfield-Mask: 0x01)                             */
#define GCR_RST1_I2C2_SHIFT                 (20UL)                    /*!< I2C2 (Bit 20)                                         */
#define GCR_RST1_I2C2_MASK                  (0x100000UL)              /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define GCR_RST1_DVS_SHIFT                  (24UL)                    /*!< DVS (Bit 24)                                          */
#define GCR_RST1_DVS_MASK                   (0x1000000UL)             /*!< DVS (Bitfield-Mask: 0x01)                             */
#define GCR_RST1_SIMO_SHIFT                 (25UL)                    /*!< SIMO (Bit 25)                                         */
#define GCR_RST1_SIMO_MASK                  (0x2000000UL)             /*!< SIMO (Bitfield-Mask: 0x01)                            */
#define GCR_RST1_CPU1_SHIFT                 (31UL)                    /*!< CPU1 (Bit 31)                                         */
#define GCR_RST1_CPU1_MASK                  (0x80000000UL)            /*!< CPU1 (Bitfield-Mask: 0x01)                            */
/* =======================================================  PCLKDIS1  ======================================================== */
#define GCR_PCLKDIS1_UART2_SHIFT            (1UL)                     /*!< UART2 (Bit 1)                                         */
#define GCR_PCLKDIS1_UART2_MASK             (0x2UL)                   /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS1_TRNG_SHIFT             (2UL)                     /*!< TRNG (Bit 2)                                          */
#define GCR_PCLKDIS1_TRNG_MASK              (0x4UL)                   /*!< TRNG (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS1_SMPHR_SHIFT            (9UL)                     /*!< SMPHR (Bit 9)                                         */
#define GCR_PCLKDIS1_SMPHR_MASK             (0x200UL)                 /*!< SMPHR (Bitfield-Mask: 0x01)                           */
#define GCR_PCLKDIS1_OWM_SHIFT              (13UL)                    /*!< OWM (Bit 13)                                          */
#define GCR_PCLKDIS1_OWM_MASK               (0x2000UL)                /*!< OWM (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS1_CRC_SHIFT              (14UL)                    /*!< CRC (Bit 14)                                          */
#define GCR_PCLKDIS1_CRC_MASK               (0x4000UL)                /*!< CRC (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS1_AES_SHIFT              (15UL)                    /*!< AES (Bit 15)                                          */
#define GCR_PCLKDIS1_AES_MASK               (0x8000UL)                /*!< AES (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS1_SPI0_SHIFT             (16UL)                    /*!< SPI0 (Bit 16)                                         */
#define GCR_PCLKDIS1_SPI0_MASK              (0x10000UL)               /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS1_PCIF_SHIFT             (18UL)                    /*!< PCIF (Bit 18)                                         */
#define GCR_PCLKDIS1_PCIF_MASK              (0x40000UL)               /*!< PCIF (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS1_I2S_SHIFT              (23UL)                    /*!< I2S (Bit 23)                                          */
#define GCR_PCLKDIS1_I2S_MASK               (0x800000UL)              /*!< I2S (Bitfield-Mask: 0x01)                             */
#define GCR_PCLKDIS1_I2C2_SHIFT             (24UL)                    /*!< I2C2 (Bit 24)                                         */
#define GCR_PCLKDIS1_I2C2_MASK              (0x1000000UL)             /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS1_WDT0_SHIFT             (27UL)                    /*!< WDT0 (Bit 27)                                         */
#define GCR_PCLKDIS1_WDT0_MASK              (0x8000000UL)             /*!< WDT0 (Bitfield-Mask: 0x01)                            */
#define GCR_PCLKDIS1_CPU1_SHIFT             (31UL)                    /*!< CPU1 (Bit 31)                                         */
#define GCR_PCLKDIS1_CPU1_MASK              (0x80000000UL)            /*!< CPU1 (Bitfield-Mask: 0x01)                            */
/* ========================================================  EVENTEN  ======================================================== */
#define GCR_EVENTEN_DMA_SHIFT               (0UL)                     /*!< DMA (Bit 0)                                           */
#define GCR_EVENTEN_DMA_MASK                (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
#define GCR_EVENTEN_RX_SHIFT                (1UL)                     /*!< RX (Bit 1)                                            */
#define GCR_EVENTEN_RX_MASK                 (0x2UL)                   /*!< RX (Bitfield-Mask: 0x01)                              */
#define GCR_EVENTEN_TX_SHIFT                (2UL)                     /*!< TX (Bit 2)                                            */
#define GCR_EVENTEN_TX_MASK                 (0x4UL)                   /*!< TX (Bitfield-Mask: 0x01)                              */
/* =======================================================  REVISION  ======================================================== */
#define GCR_REVISION_REVISION_SHIFT         (0UL)                     /*!< REVISION (Bit 0)                                      */
#define GCR_REVISION_REVISION_MASK          (0xffffUL)                /*!< REVISION (Bitfield-Mask: 0xffff)                      */
/* =========================================================  SYSIE  ========================================================= */
#define GCR_SYSIE_ICEUNLOCK_SHIFT           (0UL)                     /*!< ICEUNLOCK (Bit 0)                                     */
#define GCR_SYSIE_ICEUNLOCK_MASK            (0x1UL)                   /*!< ICEUNLOCK (Bitfield-Mask: 0x01)                       */
/* ========================================================  ECCERR  ========================================================= */
#define GCR_ECCERR_RAM_SHIFT                (0UL)                     /*!< RAM (Bit 0)                                           */
#define GCR_ECCERR_RAM_MASK                 (0x1UL)                   /*!< RAM (Bitfield-Mask: 0x01)                             */
/* ========================================================  ECCCED  ========================================================= */
#define GCR_ECCCED_RAM_SHIFT                (0UL)                     /*!< RAM (Bit 0)                                           */
#define GCR_ECCCED_RAM_MASK                 (0x1UL)                   /*!< RAM (Bitfield-Mask: 0x01)                             */
/* =========================================================  ECCIE  ========================================================= */
#define GCR_ECCIE_RAM_SHIFT                 (0UL)                     /*!< RAM (Bit 0)                                           */
#define GCR_ECCIE_RAM_MASK                  (0x1UL)                   /*!< RAM (Bitfield-Mask: 0x01)                             */
/* ========================================================  ECCADDR  ======================================================== */
#define GCR_ECCADDR_ECCERRAD_SHIFT          (0UL)                     /*!< ECCERRAD (Bit 0)                                      */
#define GCR_ECCADDR_ECCERRAD_MASK           (0xffffffffUL)            /*!< ECCERRAD (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  GPR  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            MCR                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  ECCEN  ========================================================= */
#define MCR_ECCEN_RAM0_SHIFT                (0UL)                     /*!< RAM0 (Bit 0)                                          */
#define MCR_ECCEN_RAM0_MASK                 (0x1UL)                   /*!< RAM0 (Bitfield-Mask: 0x01)                            */
/* =======================================================  IPO_MTRIM  ======================================================= */
#define MCR_IPO_MTRIM_MTRIM_SHIFT           (0UL)                     /*!< MTRIM (Bit 0)                                         */
#define MCR_IPO_MTRIM_MTRIM_MASK            (0xffUL)                  /*!< MTRIM (Bitfield-Mask: 0xff)                           */
#define MCR_IPO_MTRIM_TRIM_RANGE_SHIFT      (8UL)                     /*!< TRIM_RANGE (Bit 8)                                    */
#define MCR_IPO_MTRIM_TRIM_RANGE_MASK       (0x100UL)                 /*!< TRIM_RANGE (Bitfield-Mask: 0x01)                      */
/* =========================================================  OUTEN  ========================================================= */
#define MCR_OUTEN_SQWOUT_EN_SHIFT           (0UL)                     /*!< SQWOUT_EN (Bit 0)                                     */
#define MCR_OUTEN_SQWOUT_EN_MASK            (0x1UL)                   /*!< SQWOUT_EN (Bitfield-Mask: 0x01)                       */
#define MCR_OUTEN_PDOWN_OUT_EN_SHIFT        (1UL)                     /*!< PDOWN_OUT_EN (Bit 1)                                  */
#define MCR_OUTEN_PDOWN_OUT_EN_MASK         (0x2UL)                   /*!< PDOWN_OUT_EN (Bitfield-Mask: 0x01)                    */
/* =======================================================  CMP_CTRL  ======================================================== */
#define MCR_CMP_CTRL_EN_SHIFT               (0UL)                     /*!< EN (Bit 0)                                            */
#define MCR_CMP_CTRL_EN_MASK                (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define MCR_CMP_CTRL_POL_SHIFT              (5UL)                     /*!< POL (Bit 5)                                           */
#define MCR_CMP_CTRL_POL_MASK               (0x20UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define MCR_CMP_CTRL_INT_EN_SHIFT           (6UL)                     /*!< INT_EN (Bit 6)                                        */
#define MCR_CMP_CTRL_INT_EN_MASK            (0x40UL)                  /*!< INT_EN (Bitfield-Mask: 0x01)                          */
#define MCR_CMP_CTRL_OUT_SHIFT              (14UL)                    /*!< OUT (Bit 14)                                          */
#define MCR_CMP_CTRL_OUT_MASK               (0x4000UL)                /*!< OUT (Bitfield-Mask: 0x01)                             */
#define MCR_CMP_CTRL_INT_FL_SHIFT           (15UL)                    /*!< INT_FL (Bit 15)                                       */
#define MCR_CMP_CTRL_INT_FL_MASK            (0x8000UL)                /*!< INT_FL (Bitfield-Mask: 0x01)                          */
/* =========================================================  CTRL  ========================================================== */
#define MCR_CTRL_INRO_EN_SHIFT              (2UL)                     /*!< INRO_EN (Bit 2)                                       */
#define MCR_CTRL_INRO_EN_MASK               (0x4UL)                   /*!< INRO_EN (Bitfield-Mask: 0x01)                         */
#define MCR_CTRL_ERTCO_EN_SHIFT             (3UL)                     /*!< ERTCO_EN (Bit 3)                                      */
#define MCR_CTRL_ERTCO_EN_MASK              (0x8UL)                   /*!< ERTCO_EN (Bitfield-Mask: 0x01)                        */
#define MCR_CTRL_SIMO_CLKSCL_EN_SHIFT       (8UL)                     /*!< SIMO_CLKSCL_EN (Bit 8)                                */
#define MCR_CTRL_SIMO_CLKSCL_EN_MASK        (0x100UL)                 /*!< SIMO_CLKSCL_EN (Bitfield-Mask: 0x01)                  */
#define MCR_CTRL_SIMO_RSTD_SHIFT            (9UL)                     /*!< SIMO_RSTD (Bit 9)                                     */
#define MCR_CTRL_SIMO_RSTD_MASK             (0x200UL)                 /*!< SIMO_RSTD (Bitfield-Mask: 0x01)                       */
/* ======================================================  GPIO3_CTRL  ======================================================= */
#define MCR_GPIO3_CTRL_P30_DO_SHIFT         (0UL)                     /*!< P30_DO (Bit 0)                                        */
#define MCR_GPIO3_CTRL_P30_DO_MASK          (0x1UL)                   /*!< P30_DO (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P30_OE_SHIFT         (1UL)                     /*!< P30_OE (Bit 1)                                        */
#define MCR_GPIO3_CTRL_P30_OE_MASK          (0x2UL)                   /*!< P30_OE (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P30_PE_SHIFT         (2UL)                     /*!< P30_PE (Bit 2)                                        */
#define MCR_GPIO3_CTRL_P30_PE_MASK          (0x4UL)                   /*!< P30_PE (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P30_IN_SHIFT         (3UL)                     /*!< P30_IN (Bit 3)                                        */
#define MCR_GPIO3_CTRL_P30_IN_MASK          (0x8UL)                   /*!< P30_IN (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P31_DO_SHIFT         (4UL)                     /*!< P31_DO (Bit 4)                                        */
#define MCR_GPIO3_CTRL_P31_DO_MASK          (0x10UL)                  /*!< P31_DO (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P31_OE_SHIFT         (5UL)                     /*!< P31_OE (Bit 5)                                        */
#define MCR_GPIO3_CTRL_P31_OE_MASK          (0x20UL)                  /*!< P31_OE (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P31_PE_SHIFT         (6UL)                     /*!< P31_PE (Bit 6)                                        */
#define MCR_GPIO3_CTRL_P31_PE_MASK          (0x40UL)                  /*!< P31_PE (Bitfield-Mask: 0x01)                          */
#define MCR_GPIO3_CTRL_P31_IN_SHIFT         (7UL)                     /*!< P31_IN (Bit 7)                                        */
#define MCR_GPIO3_CTRL_P31_IN_MASK          (0x80UL)                  /*!< P31_IN (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                           LPGCR                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  RST  ========================================================== */
#define LPGCR_RST_GPIO2_SHIFT               (0UL)                     /*!< GPIO2 (Bit 0)                                         */
#define LPGCR_RST_GPIO2_MASK                (0x1UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
#define LPGCR_RST_WDT1_SHIFT                (1UL)                     /*!< WDT1 (Bit 1)                                          */
#define LPGCR_RST_WDT1_MASK                 (0x2UL)                   /*!< WDT1 (Bitfield-Mask: 0x01)                            */
#define LPGCR_RST_TMR4_SHIFT                (2UL)                     /*!< TMR4 (Bit 2)                                          */
#define LPGCR_RST_TMR4_MASK                 (0x4UL)                   /*!< TMR4 (Bitfield-Mask: 0x01)                            */
#define LPGCR_RST_TMR5_SHIFT                (3UL)                     /*!< TMR5 (Bit 3)                                          */
#define LPGCR_RST_TMR5_MASK                 (0x8UL)                   /*!< TMR5 (Bitfield-Mask: 0x01)                            */
#define LPGCR_RST_UART3_SHIFT               (4UL)                     /*!< UART3 (Bit 4)                                         */
#define LPGCR_RST_UART3_MASK                (0x10UL)                  /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define LPGCR_RST_LPCOMP_SHIFT              (6UL)                     /*!< LPCOMP (Bit 6)                                        */
#define LPGCR_RST_LPCOMP_MASK               (0x40UL)                  /*!< LPCOMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  PCLKDIS  ======================================================== */
#define LPGCR_PCLKDIS_GPIO2_SHIFT           (0UL)                     /*!< GPIO2 (Bit 0)                                         */
#define LPGCR_PCLKDIS_GPIO2_MASK            (0x1UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
#define LPGCR_PCLKDIS_WDT1_SHIFT            (1UL)                     /*!< WDT1 (Bit 1)                                          */
#define LPGCR_PCLKDIS_WDT1_MASK             (0x2UL)                   /*!< WDT1 (Bitfield-Mask: 0x01)                            */
#define LPGCR_PCLKDIS_TMR4_SHIFT            (2UL)                     /*!< TMR4 (Bit 2)                                          */
#define LPGCR_PCLKDIS_TMR4_MASK             (0x4UL)                   /*!< TMR4 (Bitfield-Mask: 0x01)                            */
#define LPGCR_PCLKDIS_TMR5_SHIFT            (3UL)                     /*!< TMR5 (Bit 3)                                          */
#define LPGCR_PCLKDIS_TMR5_MASK             (0x8UL)                   /*!< TMR5 (Bitfield-Mask: 0x01)                            */
#define LPGCR_PCLKDIS_UART3_SHIFT           (4UL)                     /*!< UART3 (Bit 4)                                         */
#define LPGCR_PCLKDIS_UART3_MASK            (0x10UL)                  /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define LPGCR_PCLKDIS_LPCOMP_SHIFT          (6UL)                     /*!< LPCOMP (Bit 6)                                        */
#define LPGCR_PCLKDIS_LPCOMP_MASK           (0x40UL)                  /*!< LPCOMP (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                           GPIO0                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  EN0  ========================================================== */
#define GPIO0_EN0_GPIO_EN_SHIFT             (0UL)                     /*!< GPIO_EN (Bit 0)                                       */
#define GPIO0_EN0_GPIO_EN_MASK              (0xffffffffUL)            /*!< GPIO_EN (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  EN0_SET  ======================================================== */
#define GPIO0_EN0_SET_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN0_SET_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  EN0_CLR  ======================================================== */
#define GPIO0_EN0_CLR_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN0_CLR_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  OUTEN  ========================================================= */
#define GPIO0_OUTEN_EN_SHIFT                (0UL)                     /*!< EN (Bit 0)                                            */
#define GPIO0_OUTEN_EN_MASK                 (0xffffffffUL)            /*!< EN (Bitfield-Mask: 0xffffffff)                        */
/* =======================================================  OUTEN_SET  ======================================================= */
#define GPIO0_OUTEN_SET_ALL_SHIFT           (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_OUTEN_SET_ALL_MASK            (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  OUTEN_CLR  ======================================================= */
#define GPIO0_OUTEN_CLR_ALL_SHIFT           (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_OUTEN_CLR_ALL_MASK            (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  OUT  ========================================================== */
#define GPIO0_OUT_GPIO_OUT_SHIFT            (0UL)                     /*!< GPIO_OUT (Bit 0)                                      */
#define GPIO0_OUT_GPIO_OUT_MASK             (0xffffffffUL)            /*!< GPIO_OUT (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  OUT_SET  ======================================================== */
#define GPIO0_OUT_SET_GPIO_OUT_SET_SHIFT    (0UL)                     /*!< GPIO_OUT_SET (Bit 0)                                  */
#define GPIO0_OUT_SET_GPIO_OUT_SET_MASK     (0xffffffffUL)            /*!< GPIO_OUT_SET (Bitfield-Mask: 0xffffffff)              */
/* ========================================================  OUT_CLR  ======================================================== */
#define GPIO0_OUT_CLR_GPIO_OUT_CLR_SHIFT    (0UL)                     /*!< GPIO_OUT_CLR (Bit 0)                                  */
#define GPIO0_OUT_CLR_GPIO_OUT_CLR_MASK     (0xffffffffUL)            /*!< GPIO_OUT_CLR (Bitfield-Mask: 0xffffffff)              */
/* ==========================================================  IN  =========================================================== */
#define GPIO0_IN_GPIO_IN_SHIFT              (0UL)                     /*!< GPIO_IN (Bit 0)                                       */
#define GPIO0_IN_GPIO_IN_MASK               (0xffffffffUL)            /*!< GPIO_IN (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  INTMODE  ======================================================== */
#define GPIO0_INTMODE_GPIO_INTMODE_SHIFT    (0UL)                     /*!< GPIO_INTMODE (Bit 0)                                  */
#define GPIO0_INTMODE_GPIO_INTMODE_MASK     (0xffffffffUL)            /*!< GPIO_INTMODE (Bitfield-Mask: 0xffffffff)              */
/* ========================================================  INTPOL  ========================================================= */
#define GPIO0_INTPOL_GPIO_INTPOL_SHIFT      (0UL)                     /*!< GPIO_INTPOL (Bit 0)                                   */
#define GPIO0_INTPOL_GPIO_INTPOL_MASK       (0xffffffffUL)            /*!< GPIO_INTPOL (Bitfield-Mask: 0xffffffff)               */
/* =========================================================  INEN  ========================================================== */
/* =========================================================  INTEN  ========================================================= */
#define GPIO0_INTEN_GPIO_INTEN_SHIFT        (0UL)                     /*!< GPIO_INTEN (Bit 0)                                    */
#define GPIO0_INTEN_GPIO_INTEN_MASK         (0xffffffffUL)            /*!< GPIO_INTEN (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  INTEN_SET  ======================================================= */
#define GPIO0_INTEN_SET_GPIO_INTEN_SET_SHIFT (0UL)                    /*!< GPIO_INTEN_SET (Bit 0)                                */
#define GPIO0_INTEN_SET_GPIO_INTEN_SET_MASK  (0xffffffffUL)           /*!< GPIO_INTEN_SET (Bitfield-Mask: 0xffffffff)            */
/* =======================================================  INTEN_CLR  ======================================================= */
#define GPIO0_INTEN_CLR_GPIO_INTEN_CLR_SHIFT (0UL)                    /*!< GPIO_INTEN_CLR (Bit 0)                                */
#define GPIO0_INTEN_CLR_GPIO_INTEN_CLR_MASK  (0xffffffffUL)           /*!< GPIO_INTEN_CLR (Bitfield-Mask: 0xffffffff)            */
/* =========================================================  INTFL  ========================================================= */
#define GPIO0_INTFL_GPIO_INTFL_SHIFT        (0UL)                     /*!< GPIO_INTFL (Bit 0)                                    */
#define GPIO0_INTFL_GPIO_INTFL_MASK         (0xffffffffUL)            /*!< GPIO_INTFL (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  INTFL_CLR  ======================================================= */
#define GPIO0_INTFL_CLR_ALL_SHIFT           (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_INTFL_CLR_ALL_MASK            (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  WKEN  ========================================================== */
#define GPIO0_WKEN_GPIO_WKEN_SHIFT          (0UL)                     /*!< GPIO_WKEN (Bit 0)                                     */
#define GPIO0_WKEN_GPIO_WKEN_MASK           (0xffffffffUL)            /*!< GPIO_WKEN (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  WKEN_SET  ======================================================== */
#define GPIO0_WKEN_SET_ALL_SHIFT            (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_WKEN_SET_ALL_MASK             (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  WKEN_CLR  ======================================================== */
#define GPIO0_WKEN_CLR_ALL_SHIFT            (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_WKEN_CLR_ALL_MASK             (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  DUALEDGE  ======================================================== */
#define GPIO0_DUALEDGE_GPIO_DUALEDGE_SHIFT  (0UL)                     /*!< GPIO_DUALEDGE (Bit 0)                                 */
#define GPIO0_DUALEDGE_GPIO_DUALEDGE_MASK   (0xffffffffUL)            /*!< GPIO_DUALEDGE (Bitfield-Mask: 0xffffffff)             */
/* =======================================================  PADCTRL0  ======================================================== */
#define GPIO0_PADCTRL0_GPIO_PADCTRL0_SHIFT  (0UL)                     /*!< GPIO_PADCTRL0 (Bit 0)                                 */
#define GPIO0_PADCTRL0_GPIO_PADCTRL0_MASK   (0xffffffffUL)            /*!< GPIO_PADCTRL0 (Bitfield-Mask: 0xffffffff)             */
/* =======================================================  PADCTRL1  ======================================================== */
#define GPIO0_PADCTRL1_GPIO_PADCTRL1_SHIFT  (0UL)                     /*!< GPIO_PADCTRL1 (Bit 0)                                 */
#define GPIO0_PADCTRL1_GPIO_PADCTRL1_MASK   (0xffffffffUL)            /*!< GPIO_PADCTRL1 (Bitfield-Mask: 0xffffffff)             */
/* ==========================================================  EN1  ========================================================== */
#define GPIO0_EN1_GPIO_EN1_SHIFT            (0UL)                     /*!< GPIO_EN1 (Bit 0)                                      */
#define GPIO0_EN1_GPIO_EN1_MASK             (0xffffffffUL)            /*!< GPIO_EN1 (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  EN1_SET  ======================================================== */
#define GPIO0_EN1_SET_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN1_SET_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  EN1_CLR  ======================================================== */
#define GPIO0_EN1_CLR_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN1_CLR_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN2  ========================================================== */
#define GPIO0_EN2_GPIO_EN2_SHIFT            (0UL)                     /*!< GPIO_EN2 (Bit 0)                                      */
#define GPIO0_EN2_GPIO_EN2_MASK             (0xffffffffUL)            /*!< GPIO_EN2 (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  EN2_SET  ======================================================== */
#define GPIO0_EN2_SET_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN2_SET_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  EN2_CLR  ======================================================== */
#define GPIO0_EN2_CLR_ALL_SHIFT             (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_EN2_CLR_ALL_MASK              (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  HYSEN  ========================================================= */
#define GPIO0_HYSEN_GPIO_HYSEN_SHIFT        (0UL)                     /*!< GPIO_HYSEN (Bit 0)                                    */
#define GPIO0_HYSEN_GPIO_HYSEN_MASK         (0xffffffffUL)            /*!< GPIO_HYSEN (Bitfield-Mask: 0xffffffff)                */
/* =========================================================  SRSEL  ========================================================= */
#define GPIO0_SRSEL_GPIO_SRSEL_SHIFT        (0UL)                     /*!< GPIO_SRSEL (Bit 0)                                    */
#define GPIO0_SRSEL_GPIO_SRSEL_MASK         (0xffffffffUL)            /*!< GPIO_SRSEL (Bitfield-Mask: 0xffffffff)                */
/* ==========================================================  DS0  ========================================================== */
#define GPIO0_DS0_GPIO_DS0_SHIFT            (0UL)                     /*!< GPIO_DS0 (Bit 0)                                      */
#define GPIO0_DS0_GPIO_DS0_MASK             (0xffffffffUL)            /*!< GPIO_DS0 (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  DS1  ========================================================== */
#define GPIO0_DS1_GPIO_DS1_SHIFT            (0UL)                     /*!< GPIO_DS1 (Bit 0)                                      */
#define GPIO0_DS1_GPIO_DS1_MASK             (0xffffffffUL)            /*!< GPIO_DS1 (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  PS  =========================================================== */
#define GPIO0_PS_ALL_SHIFT                  (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_PS_ALL_MASK                   (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  VSSEL  ========================================================= */
#define GPIO0_VSSEL_ALL_SHIFT               (0UL)                     /*!< ALL (Bit 0)                                           */
#define GPIO0_VSSEL_ALL_MASK                (0xffffffffUL)            /*!< ALL (Bitfield-Mask: 0xffffffff)                       */


/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define I2C_CTRL_EN_SHIFT                  (0UL)                     /*!< EN (Bit 0)                                            */
#define I2C_CTRL_EN_MASK                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define I2C_CTRL_MST_MODE_SHIFT            (1UL)                     /*!< MST_MODE (Bit 1)                                      */
#define I2C_CTRL_MST_MODE_MASK             (0x2UL)                   /*!< MST_MODE (Bitfield-Mask: 0x01)                        */
#define I2C_CTRL_GC_ADDR_EN_SHIFT          (2UL)                     /*!< GC_ADDR_EN (Bit 2)                                    */
#define I2C_CTRL_GC_ADDR_EN_MASK           (0x4UL)                   /*!< GC_ADDR_EN (Bitfield-Mask: 0x01)                      */
#define I2C_CTRL_IRXM_EN_SHIFT             (3UL)                     /*!< IRXM_EN (Bit 3)                                       */
#define I2C_CTRL_IRXM_EN_MASK              (0x8UL)                   /*!< IRXM_EN (Bitfield-Mask: 0x01)                         */
#define I2C_CTRL_IRXM_ACK_SHIFT            (4UL)                     /*!< IRXM_ACK (Bit 4)                                      */
#define I2C_CTRL_IRXM_ACK_MASK             (0x10UL)                  /*!< IRXM_ACK (Bitfield-Mask: 0x01)                        */
#define I2C_CTRL_SCL_OUT_SHIFT             (6UL)                     /*!< SCL_OUT (Bit 6)                                       */
#define I2C_CTRL_SCL_OUT_MASK              (0x40UL)                  /*!< SCL_OUT (Bitfield-Mask: 0x01)                         */
#define I2C_CTRL_SDA_OUT_SHIFT             (7UL)                     /*!< SDA_OUT (Bit 7)                                       */
#define I2C_CTRL_SDA_OUT_MASK              (0x80UL)                  /*!< SDA_OUT (Bitfield-Mask: 0x01)                         */
#define I2C_CTRL_SCL_SHIFT                 (8UL)                     /*!< SCL (Bit 8)                                           */
#define I2C_CTRL_SCL_MASK                  (0x100UL)                 /*!< SCL (Bitfield-Mask: 0x01)                             */
#define I2C_CTRL_SDA_SHIFT                 (9UL)                     /*!< SDA (Bit 9)                                           */
#define I2C_CTRL_SDA_MASK                  (0x200UL)                 /*!< SDA (Bitfield-Mask: 0x01)                             */
#define I2C_CTRL_BB_MODE_SHIFT             (10UL)                    /*!< BB_MODE (Bit 10)                                      */
#define I2C_CTRL_BB_MODE_MASK              (0x400UL)                 /*!< BB_MODE (Bitfield-Mask: 0x01)                         */
#define I2C_CTRL_READ_SHIFT                (11UL)                    /*!< READ (Bit 11)                                         */
#define I2C_CTRL_READ_MASK                 (0x800UL)                 /*!< READ (Bitfield-Mask: 0x01)                            */
#define I2C_CTRL_CLKSTR_DIS_SHIFT          (12UL)                    /*!< CLKSTR_DIS (Bit 12)                                   */
#define I2C_CTRL_CLKSTR_DIS_MASK           (0x1000UL)                /*!< CLKSTR_DIS (Bitfield-Mask: 0x01)                      */
#define I2C_CTRL_ONE_MST_MODE_SHIFT        (13UL)                    /*!< ONE_MST_MODE (Bit 13)                                 */
#define I2C_CTRL_ONE_MST_MODE_MASK         (0x2000UL)                /*!< ONE_MST_MODE (Bitfield-Mask: 0x01)                    */
#define I2C_CTRL_HS_EN_SHIFT               (15UL)                    /*!< HS_EN (Bit 15)                                        */
#define I2C_CTRL_HS_EN_MASK                (0x8000UL)                /*!< HS_EN (Bitfield-Mask: 0x01)                           */
/* ========================================================  STATUS  ========================================================= */
#define I2C_STATUS_BUSY_SHIFT              (0UL)                     /*!< BUSY (Bit 0)                                          */
#define I2C_STATUS_BUSY_MASK               (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS_RX_EM_SHIFT             (1UL)                     /*!< RX_EM (Bit 1)                                         */
#define I2C_STATUS_RX_EM_MASK              (0x2UL)                   /*!< RX_EM (Bitfield-Mask: 0x01)                           */
#define I2C_STATUS_RX_FULL_SHIFT           (2UL)                     /*!< RX_FULL (Bit 2)                                       */
#define I2C_STATUS_RX_FULL_MASK            (0x4UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define I2C_STATUS_TX_EM_SHIFT             (3UL)                     /*!< TX_EM (Bit 3)                                         */
#define I2C_STATUS_TX_EM_MASK              (0x8UL)                   /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define I2C_STATUS_TX_FULL_SHIFT           (4UL)                     /*!< TX_FULL (Bit 4)                                       */
#define I2C_STATUS_TX_FULL_MASK            (0x10UL)                  /*!< TX_FULL (Bitfield-Mask: 0x01)                         */
#define I2C_STATUS_MST_BUSY_SHIFT          (5UL)                     /*!< MST_BUSY (Bit 5)                                      */
#define I2C_STATUS_MST_BUSY_MASK           (0x20UL)                  /*!< MST_BUSY (Bitfield-Mask: 0x01)                        */
/* ========================================================  INTFL0  ========================================================= */
#define I2C_INTFL0_DONE_SHIFT              (0UL)                     /*!< DONE (Bit 0)                                          */
#define I2C_INTFL0_DONE_MASK               (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define I2C_INTFL0_IRXM_SHIFT              (1UL)                     /*!< IRXM (Bit 1)                                          */
#define I2C_INTFL0_IRXM_MASK               (0x2UL)                   /*!< IRXM (Bitfield-Mask: 0x01)                            */
#define I2C_INTFL0_GC_ADDR_MATCH_SHIFT     (2UL)                     /*!< GC_ADDR_MATCH (Bit 2)                                 */
#define I2C_INTFL0_GC_ADDR_MATCH_MASK      (0x4UL)                   /*!< GC_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
#define I2C_INTFL0_ADDR_MATCH_SHIFT        (3UL)                     /*!< ADDR_MATCH (Bit 3)                                    */
#define I2C_INTFL0_ADDR_MATCH_MASK         (0x8UL)                   /*!< ADDR_MATCH (Bitfield-Mask: 0x01)                      */
#define I2C_INTFL0_RX_THD_SHIFT            (4UL)                     /*!< RX_THD (Bit 4)                                        */
#define I2C_INTFL0_RX_THD_MASK             (0x10UL)                  /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define I2C_INTFL0_TX_THD_SHIFT            (5UL)                     /*!< TX_THD (Bit 5)                                        */
#define I2C_INTFL0_TX_THD_MASK             (0x20UL)                  /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define I2C_INTFL0_STOP_SHIFT              (6UL)                     /*!< STOP (Bit 6)                                          */
#define I2C_INTFL0_STOP_MASK               (0x40UL)                  /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2C_INTFL0_ADDR_ACK_SHIFT          (7UL)                     /*!< ADDR_ACK (Bit 7)                                      */
#define I2C_INTFL0_ADDR_ACK_MASK           (0x80UL)                  /*!< ADDR_ACK (Bitfield-Mask: 0x01)                        */
#define I2C_INTFL0_ARB_ERR_SHIFT           (8UL)                     /*!< ARB_ERR (Bit 8)                                       */
#define I2C_INTFL0_ARB_ERR_MASK            (0x100UL)                 /*!< ARB_ERR (Bitfield-Mask: 0x01)                         */
#define I2C_INTFL0_TO_ERR_SHIFT            (9UL)                     /*!< TO_ERR (Bit 9)                                        */
#define I2C_INTFL0_TO_ERR_MASK             (0x200UL)                 /*!< TO_ERR (Bitfield-Mask: 0x01)                          */
#define I2C_INTFL0_ADDR_NACK_ERR_SHIFT     (10UL)                    /*!< ADDR_NACK_ERR (Bit 10)                                */
#define I2C_INTFL0_ADDR_NACK_ERR_MASK      (0x400UL)                 /*!< ADDR_NACK_ERR (Bitfield-Mask: 0x01)                   */
#define I2C_INTFL0_DATA_ERR_SHIFT          (11UL)                    /*!< DATA_ERR (Bit 11)                                     */
#define I2C_INTFL0_DATA_ERR_MASK           (0x800UL)                 /*!< DATA_ERR (Bitfield-Mask: 0x01)                        */
#define I2C_INTFL0_DNR_ERR_SHIFT           (12UL)                    /*!< DNR_ERR (Bit 12)                                      */
#define I2C_INTFL0_DNR_ERR_MASK            (0x1000UL)                /*!< DNR_ERR (Bitfield-Mask: 0x01)                         */
#define I2C_INTFL0_START_ERR_SHIFT         (13UL)                    /*!< START_ERR (Bit 13)                                    */
#define I2C_INTFL0_START_ERR_MASK          (0x2000UL)                /*!< START_ERR (Bitfield-Mask: 0x01)                       */
#define I2C_INTFL0_STOP_ERR_SHIFT          (14UL)                    /*!< STOP_ERR (Bit 14)                                     */
#define I2C_INTFL0_STOP_ERR_MASK           (0x4000UL)                /*!< STOP_ERR (Bitfield-Mask: 0x01)                        */
#define I2C_INTFL0_TX_LOCKOUT_SHIFT        (15UL)                    /*!< TX_LOCKOUT (Bit 15)                                   */
#define I2C_INTFL0_TX_LOCKOUT_MASK         (0x8000UL)                /*!< TX_LOCKOUT (Bitfield-Mask: 0x01)                      */
#define I2C_INTFL0_MAMI_SHIFT              (16UL)                    /*!< MAMI (Bit 16)                                         */
#define I2C_INTFL0_MAMI_MASK               (0x3f0000UL)              /*!< MAMI (Bitfield-Mask: 0x3f)                            */
#define I2C_INTFL0_RD_ADDR_MATCH_SHIFT     (22UL)                    /*!< RD_ADDR_MATCH (Bit 22)                                */
#define I2C_INTFL0_RD_ADDR_MATCH_MASK      (0x400000UL)              /*!< RD_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
#define I2C_INTFL0_WR_ADDR_MATCH_SHIFT     (23UL)                    /*!< WR_ADDR_MATCH (Bit 23)                                */
#define I2C_INTFL0_WR_ADDR_MATCH_MASK      (0x800000UL)              /*!< WR_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
/* ========================================================  INTEN0  ========================================================= */
#define I2C_INTEN0_DONE_SHIFT              (0UL)                     /*!< DONE (Bit 0)                                          */
#define I2C_INTEN0_DONE_MASK               (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define I2C_INTEN0_IRXM_SHIFT              (1UL)                     /*!< IRXM (Bit 1)                                          */
#define I2C_INTEN0_IRXM_MASK               (0x2UL)                   /*!< IRXM (Bitfield-Mask: 0x01)                            */
#define I2C_INTEN0_GC_ADDR_MATCH_SHIFT     (2UL)                     /*!< GC_ADDR_MATCH (Bit 2)                                 */
#define I2C_INTEN0_GC_ADDR_MATCH_MASK      (0x4UL)                   /*!< GC_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
#define I2C_INTEN0_ADDR_MATCH_SHIFT        (3UL)                     /*!< ADDR_MATCH (Bit 3)                                    */
#define I2C_INTEN0_ADDR_MATCH_MASK         (0x8UL)                   /*!< ADDR_MATCH (Bitfield-Mask: 0x01)                      */
#define I2C_INTEN0_RX_THD_SHIFT            (4UL)                     /*!< RX_THD (Bit 4)                                        */
#define I2C_INTEN0_RX_THD_MASK             (0x10UL)                  /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define I2C_INTEN0_TX_THD_SHIFT            (5UL)                     /*!< TX_THD (Bit 5)                                        */
#define I2C_INTEN0_TX_THD_MASK             (0x20UL)                  /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define I2C_INTEN0_STOP_SHIFT              (6UL)                     /*!< STOP (Bit 6)                                          */
#define I2C_INTEN0_STOP_MASK               (0x40UL)                  /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2C_INTEN0_ADDR_ACK_SHIFT          (7UL)                     /*!< ADDR_ACK (Bit 7)                                      */
#define I2C_INTEN0_ADDR_ACK_MASK           (0x80UL)                  /*!< ADDR_ACK (Bitfield-Mask: 0x01)                        */
#define I2C_INTEN0_ARB_ERR_SHIFT           (8UL)                     /*!< ARB_ERR (Bit 8)                                       */
#define I2C_INTEN0_ARB_ERR_MASK            (0x100UL)                 /*!< ARB_ERR (Bitfield-Mask: 0x01)                         */
#define I2C_INTEN0_TO_ERR_SHIFT            (9UL)                     /*!< TO_ERR (Bit 9)                                        */
#define I2C_INTEN0_TO_ERR_MASK             (0x200UL)                 /*!< TO_ERR (Bitfield-Mask: 0x01)                          */
#define I2C_INTEN0_ADDR_NACK_ERR_SHIFT     (10UL)                    /*!< ADDR_NACK_ERR (Bit 10)                                */
#define I2C_INTEN0_ADDR_NACK_ERR_MASK      (0x400UL)                 /*!< ADDR_NACK_ERR (Bitfield-Mask: 0x01)                   */
#define I2C_INTEN0_DATA_ERR_SHIFT          (11UL)                    /*!< DATA_ERR (Bit 11)                                     */
#define I2C_INTEN0_DATA_ERR_MASK           (0x800UL)                 /*!< DATA_ERR (Bitfield-Mask: 0x01)                        */
#define I2C_INTEN0_DNR_ERR_SHIFT           (12UL)                    /*!< DNR_ERR (Bit 12)                                      */
#define I2C_INTEN0_DNR_ERR_MASK            (0x1000UL)                /*!< DNR_ERR (Bitfield-Mask: 0x01)                         */
#define I2C_INTEN0_START_ERR_SHIFT         (13UL)                    /*!< START_ERR (Bit 13)                                    */
#define I2C_INTEN0_START_ERR_MASK          (0x2000UL)                /*!< START_ERR (Bitfield-Mask: 0x01)                       */
#define I2C_INTEN0_STOP_ERR_SHIFT          (14UL)                    /*!< STOP_ERR (Bit 14)                                     */
#define I2C_INTEN0_STOP_ERR_MASK           (0x4000UL)                /*!< STOP_ERR (Bitfield-Mask: 0x01)                        */
#define I2C_INTEN0_TX_LOCKOUT_SHIFT        (15UL)                    /*!< TX_LOCKOUT (Bit 15)                                   */
#define I2C_INTEN0_TX_LOCKOUT_MASK         (0x8000UL)                /*!< TX_LOCKOUT (Bitfield-Mask: 0x01)                      */
#define I2C_INTEN0_MAMI_SHIFT              (16UL)                    /*!< MAMI (Bit 16)                                         */
#define I2C_INTEN0_MAMI_MASK               (0x3f0000UL)              /*!< MAMI (Bitfield-Mask: 0x3f)                            */
#define I2C_INTEN0_RD_ADDR_MATCH_SHIFT     (22UL)                    /*!< RD_ADDR_MATCH (Bit 22)                                */
#define I2C_INTEN0_RD_ADDR_MATCH_MASK      (0x400000UL)              /*!< RD_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
#define I2C_INTEN0_WR_ADDR_MATCH_SHIFT     (23UL)                    /*!< WR_ADDR_MATCH (Bit 23)                                */
#define I2C_INTEN0_WR_ADDR_MATCH_MASK      (0x800000UL)              /*!< WR_ADDR_MATCH (Bitfield-Mask: 0x01)                   */
/* ========================================================  INTFL1  ========================================================= */
#define I2C_INTFL1_RX_OV_SHIFT             (0UL)                     /*!< RX_OV (Bit 0)                                         */
#define I2C_INTFL1_RX_OV_MASK              (0x1UL)                   /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define I2C_INTFL1_TX_UN_SHIFT             (1UL)                     /*!< TX_UN (Bit 1)                                         */
#define I2C_INTFL1_TX_UN_MASK              (0x2UL)                   /*!< TX_UN (Bitfield-Mask: 0x01)                           */
#define I2C_INTFL1_START_SHIFT             (2UL)                     /*!< START (Bit 2)                                         */
#define I2C_INTFL1_START_MASK              (0x4UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTEN1  ========================================================= */
#define I2C_INTEN1_RX_OV_SHIFT             (0UL)                     /*!< RX_OV (Bit 0)                                         */
#define I2C_INTEN1_RX_OV_MASK              (0x1UL)                   /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define I2C_INTEN1_TX_UN_SHIFT             (1UL)                     /*!< TX_UN (Bit 1)                                         */
#define I2C_INTEN1_TX_UN_MASK              (0x2UL)                   /*!< TX_UN (Bitfield-Mask: 0x01)                           */
#define I2C_INTEN1_START_SHIFT             (2UL)                     /*!< START (Bit 2)                                         */
#define I2C_INTEN1_START_MASK              (0x4UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* ========================================================  FIFOLEN  ======================================================== */
#define I2C_FIFOLEN_RX_DEPTH_SHIFT         (0UL)                     /*!< RX_DEPTH (Bit 0)                                      */
#define I2C_FIFOLEN_RX_DEPTH_MASK          (0xffUL)                  /*!< RX_DEPTH (Bitfield-Mask: 0xff)                        */
#define I2C_FIFOLEN_TX_DEPTH_SHIFT         (8UL)                     /*!< TX_DEPTH (Bit 8)                                      */
#define I2C_FIFOLEN_TX_DEPTH_MASK          (0xff00UL)                /*!< TX_DEPTH (Bitfield-Mask: 0xff)                        */
/* ========================================================  RXCTRL0  ======================================================== */
#define I2C_RXCTRL0_DNR_SHIFT              (0UL)                     /*!< DNR (Bit 0)                                           */
#define I2C_RXCTRL0_DNR_MASK               (0x1UL)                   /*!< DNR (Bitfield-Mask: 0x01)                             */
#define I2C_RXCTRL0_FLUSH_SHIFT            (7UL)                     /*!< FLUSH (Bit 7)                                         */
#define I2C_RXCTRL0_FLUSH_MASK             (0x80UL)                  /*!< FLUSH (Bitfield-Mask: 0x01)                           */
#define I2C_RXCTRL0_THD_LVL_SHIFT          (8UL)                     /*!< THD_LVL (Bit 8)                                       */
#define I2C_RXCTRL0_THD_LVL_MASK           (0xf00UL)                 /*!< THD_LVL (Bitfield-Mask: 0x0f)                         */
/* ========================================================  RXCTRL1  ======================================================== */
#define I2C_RXCTRL1_CNT_SHIFT              (0UL)                     /*!< CNT (Bit 0)                                           */
#define I2C_RXCTRL1_CNT_MASK               (0xffUL)                  /*!< CNT (Bitfield-Mask: 0xff)                             */
#define I2C_RXCTRL1_LVL_SHIFT              (8UL)                     /*!< LVL (Bit 8)                                           */
#define I2C_RXCTRL1_LVL_MASK               (0xf00UL)                 /*!< LVL (Bitfield-Mask: 0x0f)                             */
/* ========================================================  TXCTRL0  ======================================================== */
#define I2C_TXCTRL0_PRELOAD_MODE_SHIFT     (0UL)                     /*!< PRELOAD_MODE (Bit 0)                                  */
#define I2C_TXCTRL0_PRELOAD_MODE_MASK      (0x1UL)                   /*!< PRELOAD_MODE (Bitfield-Mask: 0x01)                    */
#define I2C_TXCTRL0_TX_READY_MODE_SHIFT    (1UL)                     /*!< TX_READY_MODE (Bit 1)                                 */
#define I2C_TXCTRL0_TX_READY_MODE_MASK     (0x2UL)                   /*!< TX_READY_MODE (Bitfield-Mask: 0x01)                   */
#define I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_SHIFT (2UL)                    /*!< GC_ADDR_FLUSH_DIS (Bit 2)                             */
#define I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_MASK  (0x4UL)                  /*!< GC_ADDR_FLUSH_DIS (Bitfield-Mask: 0x01)               */
#define I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_SHIFT (3UL)                    /*!< WR_ADDR_FLUSH_DIS (Bit 3)                             */
#define I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_MASK  (0x8UL)                  /*!< WR_ADDR_FLUSH_DIS (Bitfield-Mask: 0x01)               */
#define I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_SHIFT (4UL)                    /*!< RD_ADDR_FLUSH_DIS (Bit 4)                             */
#define I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_MASK  (0x10UL)                 /*!< RD_ADDR_FLUSH_DIS (Bitfield-Mask: 0x01)               */
#define I2C_TXCTRL0_NACK_FLUSH_DIS_SHIFT   (5UL)                     /*!< NACK_FLUSH_DIS (Bit 5)                                */
#define I2C_TXCTRL0_NACK_FLUSH_DIS_MASK    (0x20UL)                  /*!< NACK_FLUSH_DIS (Bitfield-Mask: 0x01)                  */
#define I2C_TXCTRL0_FLUSH_SHIFT            (7UL)                     /*!< FLUSH (Bit 7)                                         */
#define I2C_TXCTRL0_FLUSH_MASK             (0x80UL)                  /*!< FLUSH (Bitfield-Mask: 0x01)                           */
#define I2C_TXCTRL0_THD_VAL_SHIFT          (8UL)                     /*!< THD_VAL (Bit 8)                                       */
#define I2C_TXCTRL0_THD_VAL_MASK           (0xf00UL)                 /*!< THD_VAL (Bitfield-Mask: 0x0f)                         */
/* ========================================================  TXCTRL1  ======================================================== */
#define I2C_TXCTRL1_PRELOAD_RDY_SHIFT      (0UL)                     /*!< PRELOAD_RDY (Bit 0)                                   */
#define I2C_TXCTRL1_PRELOAD_RDY_MASK       (0x1UL)                   /*!< PRELOAD_RDY (Bitfield-Mask: 0x01)                     */
#define I2C_TXCTRL1_LVL_SHIFT              (8UL)                     /*!< LVL (Bit 8)                                           */
#define I2C_TXCTRL1_LVL_MASK               (0xf00UL)                 /*!< LVL (Bitfield-Mask: 0x0f)                             */
/* =========================================================  FIFO  ========================================================== */
#define I2C_FIFO_DATA_SHIFT                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2C_FIFO_DATA_MASK                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* ========================================================  MSTCTRL  ======================================================== */
#define I2C_MSTCTRL_START_SHIFT            (0UL)                     /*!< START (Bit 0)                                         */
#define I2C_MSTCTRL_START_MASK             (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
#define I2C_MSTCTRL_RESTART_SHIFT          (1UL)                     /*!< RESTART (Bit 1)                                       */
#define I2C_MSTCTRL_RESTART_MASK           (0x2UL)                   /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define I2C_MSTCTRL_STOP_SHIFT             (2UL)                     /*!< STOP (Bit 2)                                          */
#define I2C_MSTCTRL_STOP_MASK              (0x4UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2C_MSTCTRL_EX_ADDR_EN_SHIFT       (7UL)                     /*!< EX_ADDR_EN (Bit 7)                                    */
#define I2C_MSTCTRL_EX_ADDR_EN_MASK        (0x80UL)                  /*!< EX_ADDR_EN (Bitfield-Mask: 0x01)                      */
/* =========================================================  CLKLO  ========================================================= */
#define I2C_CLKLO_LO_SHIFT                 (0UL)                     /*!< LO (Bit 0)                                            */
#define I2C_CLKLO_LO_MASK                  (0x1ffUL)                 /*!< LO (Bitfield-Mask: 0x1ff)                             */
/* =========================================================  CLKHI  ========================================================= */
#define I2C_CLKHI_HI_SHIFT                 (0UL)                     /*!< HI (Bit 0)                                            */
#define I2C_CLKHI_HI_MASK                  (0x1ffUL)                 /*!< HI (Bitfield-Mask: 0x1ff)                             */
/* =========================================================  HSCLK  ========================================================= */
#define I2C_HSCLK_LO_SHIFT                 (0UL)                     /*!< LO (Bit 0)                                            */
#define I2C_HSCLK_LO_MASK                  (0xffUL)                  /*!< LO (Bitfield-Mask: 0xff)                              */
#define I2C_HSCLK_HI_SHIFT                 (8UL)                     /*!< HI (Bit 8)                                            */
#define I2C_HSCLK_HI_MASK                  (0xff00UL)                /*!< HI (Bitfield-Mask: 0xff)                              */
/* ========================================================  TIMEOUT  ======================================================== */
#define I2C_TIMEOUT_SCL_TO_VAL_SHIFT       (0UL)                     /*!< SCL_TO_VAL (Bit 0)                                    */
#define I2C_TIMEOUT_SCL_TO_VAL_MASK        (0xffffUL)                /*!< SCL_TO_VAL (Bitfield-Mask: 0xffff)                    */
/* ==========================================================  DMA  ========================================================== */
#define I2C_DMA_TX_EN_SHIFT                (0UL)                     /*!< TX_EN (Bit 0)                                         */
#define I2C_DMA_TX_EN_MASK                 (0x1UL)                   /*!< TX_EN (Bitfield-Mask: 0x01)                           */
#define I2C_DMA_RX_EN_SHIFT                (1UL)                     /*!< RX_EN (Bit 1)                                         */
#define I2C_DMA_RX_EN_MASK                 (0x2UL)                   /*!< RX_EN (Bitfield-Mask: 0x01)                           */
/* =========================================================  SLAVE  ========================================================= */
#define I2C_SLAVE_ADDR_SHIFT               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define I2C_SLAVE_ADDR_MASK                (0x3ffUL)                 /*!< ADDR (Bitfield-Mask: 0x3ff)                           */
#define I2C_SLAVE_EXT_ADDR_EN_SHIFT        (15UL)                    /*!< EXT_ADDR_EN (Bit 15)                                  */
#define I2C_SLAVE_EXT_ADDR_EN_MASK         (0x8000UL)                /*!< EXT_ADDR_EN (Bitfield-Mask: 0x01)                     */


/* =========================================================================================================================== */
/* ================                                            I2S                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  CTRL0CH0  ======================================================== */
#define I2S_CTRL0CH0_LSB_FIRST_SHIFT        (1UL)                     /*!< LSB_FIRST (Bit 1)                                     */
#define I2S_CTRL0CH0_LSB_FIRST_MASK         (0x2UL)                   /*!< LSB_FIRST (Bitfield-Mask: 0x01)                       */
#define I2S_CTRL0CH0_PDM_FILT_SHIFT         (2UL)                     /*!< PDM_FILT (Bit 2)                                      */
#define I2S_CTRL0CH0_PDM_FILT_MASK          (0x4UL)                   /*!< PDM_FILT (Bitfield-Mask: 0x01)                        */
#define I2S_CTRL0CH0_PDM_EN_SHIFT           (3UL)                     /*!< PDM_EN (Bit 3)                                        */
#define I2S_CTRL0CH0_PDM_EN_MASK            (0x8UL)                   /*!< PDM_EN (Bitfield-Mask: 0x01)                          */
#define I2S_CTRL0CH0_USEDDR_SHIFT           (4UL)                     /*!< USEDDR (Bit 4)                                        */
#define I2S_CTRL0CH0_USEDDR_MASK            (0x10UL)                  /*!< USEDDR (Bitfield-Mask: 0x01)                          */
#define I2S_CTRL0CH0_PDM_INV_SHIFT          (5UL)                     /*!< PDM_INV (Bit 5)                                       */
#define I2S_CTRL0CH0_PDM_INV_MASK           (0x20UL)                  /*!< PDM_INV (Bitfield-Mask: 0x01)                         */
#define I2S_CTRL0CH0_CH_MODE_SHIFT          (6UL)                     /*!< CH_MODE (Bit 6)                                       */
#define I2S_CTRL0CH0_CH_MODE_MASK           (0xc0UL)                  /*!< CH_MODE (Bitfield-Mask: 0x03)                         */
#define I2S_CTRL0CH0_WS_POL_SHIFT           (8UL)                     /*!< WS_POL (Bit 8)                                        */
#define I2S_CTRL0CH0_WS_POL_MASK            (0x100UL)                 /*!< WS_POL (Bitfield-Mask: 0x01)                          */
#define I2S_CTRL0CH0_MSB_LOC_SHIFT          (9UL)                     /*!< MSB_LOC (Bit 9)                                       */
#define I2S_CTRL0CH0_MSB_LOC_MASK           (0x200UL)                 /*!< MSB_LOC (Bitfield-Mask: 0x01)                         */
#define I2S_CTRL0CH0_ALIGN_SHIFT            (10UL)                    /*!< ALIGN (Bit 10)                                        */
#define I2S_CTRL0CH0_ALIGN_MASK             (0x400UL)                 /*!< ALIGN (Bitfield-Mask: 0x01)                           */
#define I2S_CTRL0CH0_EXT_SEL_SHIFT          (11UL)                    /*!< EXT_SEL (Bit 11)                                      */
#define I2S_CTRL0CH0_EXT_SEL_MASK           (0x800UL)                 /*!< EXT_SEL (Bitfield-Mask: 0x01)                         */
#define I2S_CTRL0CH0_STEREO_SHIFT           (12UL)                    /*!< STEREO (Bit 12)                                       */
#define I2S_CTRL0CH0_STEREO_MASK            (0x3000UL)                /*!< STEREO (Bitfield-Mask: 0x03)                          */
#define I2S_CTRL0CH0_WSIZE_SHIFT            (14UL)                    /*!< WSIZE (Bit 14)                                        */
#define I2S_CTRL0CH0_WSIZE_MASK             (0xc000UL)                /*!< WSIZE (Bitfield-Mask: 0x03)                           */
#define I2S_CTRL0CH0_TX_EN_SHIFT            (16UL)                    /*!< TX_EN (Bit 16)                                        */
#define I2S_CTRL0CH0_TX_EN_MASK             (0x10000UL)               /*!< TX_EN (Bitfield-Mask: 0x01)                           */
#define I2S_CTRL0CH0_RX_EN_SHIFT            (17UL)                    /*!< RX_EN (Bit 17)                                        */
#define I2S_CTRL0CH0_RX_EN_MASK             (0x20000UL)               /*!< RX_EN (Bitfield-Mask: 0x01)                           */
#define I2S_CTRL0CH0_FLUSH_SHIFT            (18UL)                    /*!< FLUSH (Bit 18)                                        */
#define I2S_CTRL0CH0_FLUSH_MASK             (0x40000UL)               /*!< FLUSH (Bitfield-Mask: 0x01)                           */
#define I2S_CTRL0CH0_RST_SHIFT              (19UL)                    /*!< RST (Bit 19)                                          */
#define I2S_CTRL0CH0_RST_MASK               (0x80000UL)               /*!< RST (Bitfield-Mask: 0x01)                             */
#define I2S_CTRL0CH0_FIFO_LSB_SHIFT         (20UL)                    /*!< FIFO_LSB (Bit 20)                                     */
#define I2S_CTRL0CH0_FIFO_LSB_MASK          (0x100000UL)              /*!< FIFO_LSB (Bitfield-Mask: 0x01)                        */
#define I2S_CTRL0CH0_RX_THD_VAL_SHIFT       (24UL)                    /*!< RX_THD_VAL (Bit 24)                                   */
#define I2S_CTRL0CH0_RX_THD_VAL_MASK        (0xff000000UL)            /*!< RX_THD_VAL (Bitfield-Mask: 0xff)                      */
/* =======================================================  CTRL1CH0  ======================================================== */
#define I2S_CTRL1CH0_BITS_WORD_SHIFT        (0UL)                     /*!< BITS_WORD (Bit 0)                                     */
#define I2S_CTRL1CH0_BITS_WORD_MASK         (0x1fUL)                  /*!< BITS_WORD (Bitfield-Mask: 0x1f)                       */
#define I2S_CTRL1CH0_EN_SHIFT               (8UL)                     /*!< EN (Bit 8)                                            */
#define I2S_CTRL1CH0_EN_MASK                (0x100UL)                 /*!< EN (Bitfield-Mask: 0x01)                              */
#define I2S_CTRL1CH0_SMP_SIZE_SHIFT         (9UL)                     /*!< SMP_SIZE (Bit 9)                                      */
#define I2S_CTRL1CH0_SMP_SIZE_MASK          (0x3e00UL)                /*!< SMP_SIZE (Bitfield-Mask: 0x1f)                        */
#define I2S_CTRL1CH0_ADJUST_SHIFT           (15UL)                    /*!< ADJUST (Bit 15)                                       */
#define I2S_CTRL1CH0_ADJUST_MASK            (0x8000UL)                /*!< ADJUST (Bitfield-Mask: 0x01)                          */
#define I2S_CTRL1CH0_CLKDIV_SHIFT           (16UL)                    /*!< CLKDIV (Bit 16)                                       */
#define I2S_CTRL1CH0_CLKDIV_MASK            (0xffff0000UL)            /*!< CLKDIV (Bitfield-Mask: 0xffff)                        */
/* ========================================================  FILTCH0  ======================================================== */
/* ========================================================  DMACH0  ========================================================= */
#define I2S_DMACH0_DMA_TX_THD_VAL_SHIFT     (0UL)                     /*!< DMA_TX_THD_VAL (Bit 0)                                */
#define I2S_DMACH0_DMA_TX_THD_VAL_MASK      (0x7fUL)                  /*!< DMA_TX_THD_VAL (Bitfield-Mask: 0x7f)                  */
#define I2S_DMACH0_DMA_TX_EN_SHIFT          (7UL)                     /*!< DMA_TX_EN (Bit 7)                                     */
#define I2S_DMACH0_DMA_TX_EN_MASK           (0x80UL)                  /*!< DMA_TX_EN (Bitfield-Mask: 0x01)                       */
#define I2S_DMACH0_DMA_RX_THD_VAL_SHIFT     (8UL)                     /*!< DMA_RX_THD_VAL (Bit 8)                                */
#define I2S_DMACH0_DMA_RX_THD_VAL_MASK      (0x7f00UL)                /*!< DMA_RX_THD_VAL (Bitfield-Mask: 0x7f)                  */
#define I2S_DMACH0_DMA_RX_EN_SHIFT          (15UL)                    /*!< DMA_RX_EN (Bit 15)                                    */
#define I2S_DMACH0_DMA_RX_EN_MASK           (0x8000UL)                /*!< DMA_RX_EN (Bitfield-Mask: 0x01)                       */
#define I2S_DMACH0_TX_LVL_SHIFT             (16UL)                    /*!< TX_LVL (Bit 16)                                       */
#define I2S_DMACH0_TX_LVL_MASK              (0xff0000UL)              /*!< TX_LVL (Bitfield-Mask: 0xff)                          */
#define I2S_DMACH0_RX_LVL_SHIFT             (24UL)                    /*!< RX_LVL (Bit 24)                                       */
#define I2S_DMACH0_RX_LVL_MASK              (0xff000000UL)            /*!< RX_LVL (Bitfield-Mask: 0xff)                          */
/* ========================================================  FIFOCH0  ======================================================== */
#define I2S_FIFOCH0_DATA_SHIFT              (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2S_FIFOCH0_DATA_MASK               (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  INTFL  ========================================================= */
#define I2S_INTFL_RX_OV_CH0_SHIFT           (0UL)                     /*!< RX_OV_CH0 (Bit 0)                                     */
#define I2S_INTFL_RX_OV_CH0_MASK            (0x1UL)                   /*!< RX_OV_CH0 (Bitfield-Mask: 0x01)                       */
#define I2S_INTFL_RX_THD_CH0_SHIFT          (1UL)                     /*!< RX_THD_CH0 (Bit 1)                                    */
#define I2S_INTFL_RX_THD_CH0_MASK           (0x2UL)                   /*!< RX_THD_CH0 (Bitfield-Mask: 0x01)                      */
#define I2S_INTFL_TX_OB_CH0_SHIFT           (2UL)                     /*!< TX_OB_CH0 (Bit 2)                                     */
#define I2S_INTFL_TX_OB_CH0_MASK            (0x4UL)                   /*!< TX_OB_CH0 (Bitfield-Mask: 0x01)                       */
#define I2S_INTFL_TX_HE_CH0_SHIFT           (3UL)                     /*!< TX_HE_CH0 (Bit 3)                                     */
#define I2S_INTFL_TX_HE_CH0_MASK            (0x8UL)                   /*!< TX_HE_CH0 (Bitfield-Mask: 0x01)                       */
/* =========================================================  INTEN  ========================================================= */
#define I2S_INTEN_RX_OV_CH0_SHIFT           (0UL)                     /*!< RX_OV_CH0 (Bit 0)                                     */
#define I2S_INTEN_RX_OV_CH0_MASK            (0x1UL)                   /*!< RX_OV_CH0 (Bitfield-Mask: 0x01)                       */
#define I2S_INTEN_RX_THD_CH0_SHIFT          (1UL)                     /*!< RX_THD_CH0 (Bit 1)                                    */
#define I2S_INTEN_RX_THD_CH0_MASK           (0x2UL)                   /*!< RX_THD_CH0 (Bitfield-Mask: 0x01)                      */
#define I2S_INTEN_TX_OB_CH0_SHIFT           (2UL)                     /*!< TX_OB_CH0 (Bit 2)                                     */
#define I2S_INTEN_TX_OB_CH0_MASK            (0x4UL)                   /*!< TX_OB_CH0 (Bitfield-Mask: 0x01)                       */
#define I2S_INTEN_TX_HE_CH0_SHIFT           (3UL)                     /*!< TX_HE_CH0 (Bit 3)                                     */
#define I2S_INTEN_TX_HE_CH0_MASK            (0x8UL)                   /*!< TX_HE_CH0 (Bitfield-Mask: 0x01)                       */
/* =======================================================  EXTSETUP  ======================================================== */
#define I2S_EXTSETUP_EXT_BITS_WORD_SHIFT    (0UL)                     /*!< EXT_BITS_WORD (Bit 0)                                 */
#define I2S_EXTSETUP_EXT_BITS_WORD_MASK     (0x1fUL)                  /*!< EXT_BITS_WORD (Bitfield-Mask: 0x1f)                   */
/* =========================================================  WKEN  ========================================================== */
/* =========================================================  WKFL  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            OWM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define OWM_CFG_LONG_LINE_MODE_SHIFT        (0UL)                     /*!< long_line_mode (Bit 0)                                */
#define OWM_CFG_LONG_LINE_MODE_MASK         (0x1UL)                   /*!< long_line_mode (Bitfield-Mask: 0x01)                  */
#define OWM_CFG_FORCE_PRES_DET_SHIFT        (1UL)                     /*!< force_pres_det (Bit 1)                                */
#define OWM_CFG_FORCE_PRES_DET_MASK         (0x2UL)                   /*!< force_pres_det (Bitfield-Mask: 0x01)                  */
#define OWM_CFG_BIT_BANG_EN_SHIFT           (2UL)                     /*!< bit_bang_en (Bit 2)                                   */
#define OWM_CFG_BIT_BANG_EN_MASK            (0x4UL)                   /*!< bit_bang_en (Bitfield-Mask: 0x01)                     */
#define OWM_CFG_EXT_PULLUP_MODE_SHIFT       (3UL)                     /*!< ext_pullup_mode (Bit 3)                               */
#define OWM_CFG_EXT_PULLUP_MODE_MASK        (0x8UL)                   /*!< ext_pullup_mode (Bitfield-Mask: 0x01)                 */
#define OWM_CFG_EXT_PULLUP_ENABLE_SHIFT     (4UL)                     /*!< ext_pullup_enable (Bit 4)                             */
#define OWM_CFG_EXT_PULLUP_ENABLE_MASK      (0x10UL)                  /*!< ext_pullup_enable (Bitfield-Mask: 0x01)               */
#define OWM_CFG_SINGLE_BIT_MODE_SHIFT       (5UL)                     /*!< single_bit_mode (Bit 5)                               */
#define OWM_CFG_SINGLE_BIT_MODE_MASK        (0x20UL)                  /*!< single_bit_mode (Bitfield-Mask: 0x01)                 */
#define OWM_CFG_OVERDRIVE_SHIFT             (6UL)                     /*!< overdrive (Bit 6)                                     */
#define OWM_CFG_OVERDRIVE_MASK              (0x40UL)                  /*!< overdrive (Bitfield-Mask: 0x01)                       */
#define OWM_CFG_INT_PULLUP_ENABLE_SHIFT     (7UL)                     /*!< int_pullup_enable (Bit 7)                             */
#define OWM_CFG_INT_PULLUP_ENABLE_MASK      (0x80UL)                  /*!< int_pullup_enable (Bitfield-Mask: 0x01)               */
/* ======================================================  CLK_DIV_1US  ====================================================== */
#define OWM_CLK_DIV_1US_DIVISOR_SHIFT       (0UL)                     /*!< divisor (Bit 0)                                       */
#define OWM_CLK_DIV_1US_DIVISOR_MASK        (0xffUL)                  /*!< divisor (Bitfield-Mask: 0xff)                         */
/* =======================================================  CTRL_STAT  ======================================================= */
#define OWM_CTRL_STAT_START_OW_RESET_SHIFT  (0UL)                     /*!< start_ow_reset (Bit 0)                                */
#define OWM_CTRL_STAT_START_OW_RESET_MASK   (0x1UL)                   /*!< start_ow_reset (Bitfield-Mask: 0x01)                  */
#define OWM_CTRL_STAT_SRA_MODE_SHIFT        (1UL)                     /*!< sra_mode (Bit 1)                                      */
#define OWM_CTRL_STAT_SRA_MODE_MASK         (0x2UL)                   /*!< sra_mode (Bitfield-Mask: 0x01)                        */
#define OWM_CTRL_STAT_BIT_BANG_OE_SHIFT     (2UL)                     /*!< bit_bang_oe (Bit 2)                                   */
#define OWM_CTRL_STAT_BIT_BANG_OE_MASK      (0x4UL)                   /*!< bit_bang_oe (Bitfield-Mask: 0x01)                     */
#define OWM_CTRL_STAT_OW_INPUT_SHIFT        (3UL)                     /*!< ow_input (Bit 3)                                      */
#define OWM_CTRL_STAT_OW_INPUT_MASK         (0x8UL)                   /*!< ow_input (Bitfield-Mask: 0x01)                        */
#define OWM_CTRL_STAT_OD_SPEC_MODE_SHIFT    (4UL)                     /*!< od_spec_mode (Bit 4)                                  */
#define OWM_CTRL_STAT_OD_SPEC_MODE_MASK     (0x10UL)                  /*!< od_spec_mode (Bitfield-Mask: 0x01)                    */
#define OWM_CTRL_STAT_EXT_PULLUP_POL_SHIFT  (5UL)                     /*!< ext_pullup_pol (Bit 5)                                */
#define OWM_CTRL_STAT_EXT_PULLUP_POL_MASK   (0x20UL)                  /*!< ext_pullup_pol (Bitfield-Mask: 0x01)                  */
#define OWM_CTRL_STAT_PRESENCE_DETECT_SHIFT (7UL)                     /*!< presence_detect (Bit 7)                               */
#define OWM_CTRL_STAT_PRESENCE_DETECT_MASK  (0x80UL)                  /*!< presence_detect (Bitfield-Mask: 0x01)                 */
/* =========================================================  DATA  ========================================================== */
#define OWM_DATA_TX_RX_SHIFT                (0UL)                     /*!< tx_rx (Bit 0)                                         */
#define OWM_DATA_TX_RX_MASK                 (0xffUL)                  /*!< tx_rx (Bitfield-Mask: 0xff)                           */
/* =========================================================  INTFL  ========================================================= */
#define OWM_INTFL_OW_RESET_DONE_SHIFT       (0UL)                     /*!< ow_reset_done (Bit 0)                                 */
#define OWM_INTFL_OW_RESET_DONE_MASK        (0x1UL)                   /*!< ow_reset_done (Bitfield-Mask: 0x01)                   */
#define OWM_INTFL_TX_DATA_EMPTY_SHIFT       (1UL)                     /*!< tx_data_empty (Bit 1)                                 */
#define OWM_INTFL_TX_DATA_EMPTY_MASK        (0x2UL)                   /*!< tx_data_empty (Bitfield-Mask: 0x01)                   */
#define OWM_INTFL_RX_DATA_READY_SHIFT       (2UL)                     /*!< rx_data_ready (Bit 2)                                 */
#define OWM_INTFL_RX_DATA_READY_MASK        (0x4UL)                   /*!< rx_data_ready (Bitfield-Mask: 0x01)                   */
#define OWM_INTFL_LINE_SHORT_SHIFT          (3UL)                     /*!< line_short (Bit 3)                                    */
#define OWM_INTFL_LINE_SHORT_MASK           (0x8UL)                   /*!< line_short (Bitfield-Mask: 0x01)                      */
#define OWM_INTFL_LINE_LOW_SHIFT            (4UL)                     /*!< line_low (Bit 4)                                      */
#define OWM_INTFL_LINE_LOW_MASK             (0x10UL)                  /*!< line_low (Bitfield-Mask: 0x01)                        */
/* =========================================================  INTEN  ========================================================= */
#define OWM_INTEN_OW_RESET_DONE_SHIFT       (0UL)                     /*!< ow_reset_done (Bit 0)                                 */
#define OWM_INTEN_OW_RESET_DONE_MASK        (0x1UL)                   /*!< ow_reset_done (Bitfield-Mask: 0x01)                   */
#define OWM_INTEN_TX_DATA_EMPTY_SHIFT       (1UL)                     /*!< tx_data_empty (Bit 1)                                 */
#define OWM_INTEN_TX_DATA_EMPTY_MASK        (0x2UL)                   /*!< tx_data_empty (Bitfield-Mask: 0x01)                   */
#define OWM_INTEN_RX_DATA_READY_SHIFT       (2UL)                     /*!< rx_data_ready (Bit 2)                                 */
#define OWM_INTEN_RX_DATA_READY_MASK        (0x4UL)                   /*!< rx_data_ready (Bitfield-Mask: 0x01)                   */
#define OWM_INTEN_LINE_SHORT_SHIFT          (3UL)                     /*!< line_short (Bit 3)                                    */
#define OWM_INTEN_LINE_SHORT_MASK           (0x8UL)                   /*!< line_short (Bitfield-Mask: 0x01)                      */
#define OWM_INTEN_LINE_LOW_SHIFT            (4UL)                     /*!< line_low (Bit 4)                                      */
#define OWM_INTEN_LINE_LOW_MASK             (0x10UL)                  /*!< line_low (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                            PTG                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  ENABLE  ========================================================= */
#define PTG_ENABLE_PT0_SHIFT                (0UL)                     /*!< pt0 (Bit 0)                                           */
#define PTG_ENABLE_PT0_MASK                 (0x1UL)                   /*!< pt0 (Bitfield-Mask: 0x01)                             */
#define PTG_ENABLE_PT1_SHIFT                (1UL)                     /*!< pt1 (Bit 1)                                           */
#define PTG_ENABLE_PT1_MASK                 (0x2UL)                   /*!< pt1 (Bitfield-Mask: 0x01)                             */
#define PTG_ENABLE_PT2_SHIFT                (2UL)                     /*!< pt2 (Bit 2)                                           */
#define PTG_ENABLE_PT2_MASK                 (0x4UL)                   /*!< pt2 (Bitfield-Mask: 0x01)                             */
#define PTG_ENABLE_PT3_SHIFT                (3UL)                     /*!< pt3 (Bit 3)                                           */
#define PTG_ENABLE_PT3_MASK                 (0x8UL)                   /*!< pt3 (Bitfield-Mask: 0x01)                             */
/* ========================================================  RESYNC  ========================================================= */
#define PTG_RESYNC_PT0_SHIFT                (0UL)                     /*!< pt0 (Bit 0)                                           */
#define PTG_RESYNC_PT0_MASK                 (0x1UL)                   /*!< pt0 (Bitfield-Mask: 0x01)                             */
#define PTG_RESYNC_PT1_SHIFT                (1UL)                     /*!< pt1 (Bit 1)                                           */
#define PTG_RESYNC_PT1_MASK                 (0x2UL)                   /*!< pt1 (Bitfield-Mask: 0x01)                             */
#define PTG_RESYNC_PT2_SHIFT                (2UL)                     /*!< pt2 (Bit 2)                                           */
#define PTG_RESYNC_PT2_MASK                 (0x4UL)                   /*!< pt2 (Bitfield-Mask: 0x01)                             */
#define PTG_RESYNC_PT3_SHIFT                (3UL)                     /*!< pt3 (Bit 3)                                           */
#define PTG_RESYNC_PT3_MASK                 (0x8UL)                   /*!< pt3 (Bitfield-Mask: 0x01)                             */
/* =========================================================  INTFL  ========================================================= */
#define PTG_INTFL_PT0_SHIFT                 (0UL)                     /*!< pt0 (Bit 0)                                           */
#define PTG_INTFL_PT0_MASK                  (0x1UL)                   /*!< pt0 (Bitfield-Mask: 0x01)                             */
#define PTG_INTFL_PT1_SHIFT                 (1UL)                     /*!< pt1 (Bit 1)                                           */
#define PTG_INTFL_PT1_MASK                  (0x2UL)                   /*!< pt1 (Bitfield-Mask: 0x01)                             */
#define PTG_INTFL_PT2_SHIFT                 (2UL)                     /*!< pt2 (Bit 2)                                           */
#define PTG_INTFL_PT2_MASK                  (0x4UL)                   /*!< pt2 (Bitfield-Mask: 0x01)                             */
#define PTG_INTFL_PT3_SHIFT                 (3UL)                     /*!< pt3 (Bit 3)                                           */
#define PTG_INTFL_PT3_MASK                  (0x8UL)                   /*!< pt3 (Bitfield-Mask: 0x01)                             */
/* =========================================================  INTEN  ========================================================= */
#define PTG_INTEN_PT0_SHIFT                 (0UL)                     /*!< pt0 (Bit 0)                                           */
#define PTG_INTEN_PT0_MASK                  (0x1UL)                   /*!< pt0 (Bitfield-Mask: 0x01)                             */
#define PTG_INTEN_PT1_SHIFT                 (1UL)                     /*!< pt1 (Bit 1)                                           */
#define PTG_INTEN_PT1_MASK                  (0x2UL)                   /*!< pt1 (Bitfield-Mask: 0x01)                             */
#define PTG_INTEN_PT2_SHIFT                 (2UL)                     /*!< pt2 (Bit 2)                                           */
#define PTG_INTEN_PT2_MASK                  (0x4UL)                   /*!< pt2 (Bitfield-Mask: 0x01)                             */
#define PTG_INTEN_PT3_SHIFT                 (3UL)                     /*!< pt3 (Bit 3)                                           */
#define PTG_INTEN_PT3_MASK                  (0x8UL)                   /*!< pt3 (Bitfield-Mask: 0x01)                             */
/* ========================================================  SAFE_EN  ======================================================== */
#define PTG_SAFE_EN_PT0_SHIFT               (0UL)                     /*!< PT0 (Bit 0)                                           */
#define PTG_SAFE_EN_PT0_MASK                (0x1UL)                   /*!< PT0 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_EN_PT1_SHIFT               (1UL)                     /*!< PT1 (Bit 1)                                           */
#define PTG_SAFE_EN_PT1_MASK                (0x2UL)                   /*!< PT1 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_EN_PT2_SHIFT               (2UL)                     /*!< PT2 (Bit 2)                                           */
#define PTG_SAFE_EN_PT2_MASK                (0x4UL)                   /*!< PT2 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_EN_PT3_SHIFT               (3UL)                     /*!< PT3 (Bit 3)                                           */
#define PTG_SAFE_EN_PT3_MASK                (0x8UL)                   /*!< PT3 (Bitfield-Mask: 0x01)                             */
/* =======================================================  SAFE_DIS  ======================================================== */
#define PTG_SAFE_DIS_PT0_SHIFT              (0UL)                     /*!< PT0 (Bit 0)                                           */
#define PTG_SAFE_DIS_PT0_MASK               (0x1UL)                   /*!< PT0 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_DIS_PT1_SHIFT              (1UL)                     /*!< PT1 (Bit 1)                                           */
#define PTG_SAFE_DIS_PT1_MASK               (0x2UL)                   /*!< PT1 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_DIS_PT2_SHIFT              (2UL)                     /*!< PT2 (Bit 2)                                           */
#define PTG_SAFE_DIS_PT2_MASK               (0x4UL)                   /*!< PT2 (Bitfield-Mask: 0x01)                             */
#define PTG_SAFE_DIS_PT3_SHIFT              (3UL)                     /*!< PT3 (Bit 3)                                           */
#define PTG_SAFE_DIS_PT3_MASK               (0x8UL)                   /*!< PT3 (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            PT                                             ================ */
/* =========================================================================================================================== */

/* ======================================================  RATE_LENGTH  ====================================================== */
#define PT_RATE_LENGTH_RATE_CONTROL_SHIFT   (0UL)                     /*!< rate_control (Bit 0)                                  */
#define PT_RATE_LENGTH_RATE_CONTROL_MASK    (0x7ffffffUL)             /*!< rate_control (Bitfield-Mask: 0x7ffffff)               */
#define PT_RATE_LENGTH_MODE_SHIFT           (27UL)                    /*!< mode (Bit 27)                                         */
#define PT_RATE_LENGTH_MODE_MASK            (0xf8000000UL)            /*!< mode (Bitfield-Mask: 0x1f)                            */
/* =========================================================  TRAIN  ========================================================= */
/* =========================================================  LOOP  ========================================================== */
#define PT_LOOP_COUNT_SHIFT                 (0UL)                     /*!< count (Bit 0)                                         */
#define PT_LOOP_COUNT_MASK                  (0xffffUL)                /*!< count (Bitfield-Mask: 0xffff)                         */
#define PT_LOOP_DELAY_SHIFT                 (16UL)                    /*!< delay (Bit 16)                                        */
#define PT_LOOP_DELAY_MASK                  (0xfff0000UL)             /*!< delay (Bitfield-Mask: 0xfff)                          */
/* ========================================================  RESTART  ======================================================== */
#define PT_RESTART_PT_X_SELECT_SHIFT        (0UL)                     /*!< pt_x_select (Bit 0)                                   */
#define PT_RESTART_PT_X_SELECT_MASK         (0x1fUL)                  /*!< pt_x_select (Bitfield-Mask: 0x1f)                     */
#define PT_RESTART_ON_PT_X_LOOP_EXIT_SHIFT  (7UL)                     /*!< on_pt_x_loop_exit (Bit 7)                             */
#define PT_RESTART_ON_PT_X_LOOP_EXIT_MASK   (0x80UL)                  /*!< on_pt_x_loop_exit (Bitfield-Mask: 0x01)               */
#define PT_RESTART_PT_Y_SELECT_SHIFT        (8UL)                     /*!< pt_y_select (Bit 8)                                   */
#define PT_RESTART_PT_Y_SELECT_MASK         (0x1f00UL)                /*!< pt_y_select (Bitfield-Mask: 0x1f)                     */
#define PT_RESTART_ON_PT_Y_LOOP_EXIT_SHIFT  (15UL)                    /*!< on_pt_y_loop_exit (Bit 15)                            */
#define PT_RESTART_ON_PT_Y_LOOP_EXIT_MASK   (0x8000UL)                /*!< on_pt_y_loop_exit (Bitfield-Mask: 0x01)               */


/* =========================================================================================================================== */
/* ================                                           ICC0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INFO  ========================================================== */
#define ICC_INFO_RELNUM_SHIFT              (0UL)                     /*!< RELNUM (Bit 0)                                        */
#define ICC_INFO_RELNUM_MASK               (0x3fUL)                  /*!< RELNUM (Bitfield-Mask: 0x3f)                          */
#define ICC_INFO_PARTNUM_SHIFT             (6UL)                     /*!< PARTNUM (Bit 6)                                       */
#define ICC_INFO_PARTNUM_MASK              (0x3c0UL)                 /*!< PARTNUM (Bitfield-Mask: 0x0f)                         */
#define ICC_INFO_ID_SHIFT                  (10UL)                    /*!< ID (Bit 10)                                           */
#define ICC_INFO_ID_MASK                   (0xfc00UL)                /*!< ID (Bitfield-Mask: 0x3f)                              */
/* ==========================================================  SZ  =========================================================== */
#define ICC_SZ_CCH_SHIFT                   (0UL)                     /*!< CCH (Bit 0)                                           */
#define ICC_SZ_CCH_MASK                    (0xffffUL)                /*!< CCH (Bitfield-Mask: 0xffff)                           */
#define ICC_SZ_MEM_SHIFT                   (16UL)                    /*!< MEM (Bit 16)                                          */
#define ICC_SZ_MEM_MASK                    (0xffff0000UL)            /*!< MEM (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CTRL  ========================================================== */
#define ICC_CTRL_EN_SHIFT                  (0UL)                     /*!< EN (Bit 0)                                            */
#define ICC_CTRL_EN_MASK                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define ICC_CTRL_RDY_SHIFT                 (16UL)                    /*!< RDY (Bit 16)                                          */
#define ICC_CTRL_RDY_MASK                  (0x10000UL)               /*!< RDY (Bitfield-Mask: 0x01)                             */
/* ======================================================  INVALIDATE  ======================================================= */
#define ICC_INVALIDATE_INVALID_SHIFT       (0UL)                     /*!< INVALID (Bit 0)                                       */
#define ICC_INVALIDATE_INVALID_MASK        (0xffffffffUL)            /*!< INVALID (Bitfield-Mask: 0xffffffff)                   */


/* =========================================================================================================================== */
/* ================                                          PWRSEQ                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  LPCN  ========================================================== */
#define PWRSEQ_LPCN_RAMRET0_SHIFT           (0UL)                     /*!< RAMRET0 (Bit 0)                                       */
#define PWRSEQ_LPCN_RAMRET0_MASK            (0x1UL)                   /*!< RAMRET0 (Bitfield-Mask: 0x01)                         */
#define PWRSEQ_LPCN_RAMRET1_SHIFT           (1UL)                     /*!< RAMRET1 (Bit 1)                                       */
#define PWRSEQ_LPCN_RAMRET1_MASK            (0x2UL)                   /*!< RAMRET1 (Bitfield-Mask: 0x01)                         */
#define PWRSEQ_LPCN_RAMRET2_SHIFT           (2UL)                     /*!< RAMRET2 (Bit 2)                                       */
#define PWRSEQ_LPCN_RAMRET2_MASK            (0x4UL)                   /*!< RAMRET2 (Bitfield-Mask: 0x01)                         */
#define PWRSEQ_LPCN_RAMRET3_SHIFT           (3UL)                     /*!< RAMRET3 (Bit 3)                                       */
#define PWRSEQ_LPCN_RAMRET3_MASK            (0x8UL)                   /*!< RAMRET3 (Bitfield-Mask: 0x01)                         */
#define PWRSEQ_LPCN_LPMCLKSEL_SHIFT         (8UL)                     /*!< LPMCLKSEL (Bit 8)                                     */
#define PWRSEQ_LPCN_LPMCLKSEL_MASK          (0x100UL)                 /*!< LPMCLKSEL (Bitfield-Mask: 0x01)                       */
#define PWRSEQ_LPCN_LPMFAST_SHIFT           (9UL)                     /*!< LPMFAST (Bit 9)                                       */
#define PWRSEQ_LPCN_LPMFAST_MASK            (0x200UL)                 /*!< LPMFAST (Bitfield-Mask: 0x01)                         */
#define PWRSEQ_LPCN_BG_DIS_SHIFT            (11UL)                    /*!< BG_DIS (Bit 11)                                       */
#define PWRSEQ_LPCN_BG_DIS_MASK             (0x800UL)                 /*!< BG_DIS (Bitfield-Mask: 0x01)                          */
#define PWRSEQ_LPCN_LPWKST_CLR_SHIFT        (31UL)                    /*!< LPWKST_CLR (Bit 31)                                   */
#define PWRSEQ_LPCN_LPWKST_CLR_MASK         (0x80000000UL)            /*!< LPWKST_CLR (Bitfield-Mask: 0x01)                      */
/* ========================================================  LPWKST0  ======================================================== */
#define PWRSEQ_LPWKST0_WAKEST_SHIFT         (0UL)                     /*!< WAKEST (Bit 0)                                        */
#define PWRSEQ_LPWKST0_WAKEST_MASK          (0x1UL)                   /*!< WAKEST (Bitfield-Mask: 0x01)                          */
/* ========================================================  LPWKEN0  ======================================================== */
#define PWRSEQ_LPWKEN0_WAKEEN_SHIFT         (0UL)                     /*!< WAKEEN (Bit 0)                                        */
#define PWRSEQ_LPWKEN0_WAKEEN_MASK          (0x7fffffffUL)            /*!< WAKEEN (Bitfield-Mask: 0x7fffffff)                    */
/* ========================================================  LPWKST1  ======================================================== */
#define PWRSEQ_LPWKST1_WAKEST_SHIFT         (0UL)                     /*!< WAKEST (Bit 0)                                        */
#define PWRSEQ_LPWKST1_WAKEST_MASK          (0x1UL)                   /*!< WAKEST (Bitfield-Mask: 0x01)                          */
/* ========================================================  LPWKEN1  ======================================================== */
#define PWRSEQ_LPWKEN1_WAKEEN_SHIFT         (0UL)                     /*!< WAKEEN (Bit 0)                                        */
#define PWRSEQ_LPWKEN1_WAKEEN_MASK          (0x7fffffffUL)            /*!< WAKEEN (Bitfield-Mask: 0x7fffffff)                    */
/* ========================================================  LPWKST2  ======================================================== */
#define PWRSEQ_LPWKST2_WAKEST_SHIFT         (0UL)                     /*!< WAKEST (Bit 0)                                        */
#define PWRSEQ_LPWKST2_WAKEST_MASK          (0x1UL)                   /*!< WAKEST (Bitfield-Mask: 0x01)                          */
/* ========================================================  LPWKEN2  ======================================================== */
#define PWRSEQ_LPWKEN2_WAKEEN_SHIFT         (0UL)                     /*!< WAKEEN (Bit 0)                                        */
#define PWRSEQ_LPWKEN2_WAKEEN_MASK          (0x7fffffffUL)            /*!< WAKEEN (Bitfield-Mask: 0x7fffffff)                    */
/* ========================================================  LPWKST3  ======================================================== */
#define PWRSEQ_LPWKST3_WAKEST_SHIFT         (0UL)                     /*!< WAKEST (Bit 0)                                        */
#define PWRSEQ_LPWKST3_WAKEST_MASK          (0x1UL)                   /*!< WAKEST (Bitfield-Mask: 0x01)                          */
/* ========================================================  LPWKEN3  ======================================================== */
#define PWRSEQ_LPWKEN3_WAKEEN_SHIFT         (0UL)                     /*!< WAKEEN (Bit 0)                                        */
#define PWRSEQ_LPWKEN3_WAKEEN_MASK          (0x7fffffffUL)            /*!< WAKEEN (Bitfield-Mask: 0x7fffffff)                    */
/* ========================================================  LPPWST  ========================================================= */
#define PWRSEQ_LPPWST_AINCOMP0_SHIFT        (4UL)                     /*!< AINCOMP0 (Bit 4)                                      */
#define PWRSEQ_LPPWST_AINCOMP0_MASK         (0x10UL)                  /*!< AINCOMP0 (Bitfield-Mask: 0x01)                        */
#define PWRSEQ_LPPWST_BACKUP_SHIFT          (16UL)                    /*!< BACKUP (Bit 16)                                       */
#define PWRSEQ_LPPWST_BACKUP_MASK           (0x10000UL)               /*!< BACKUP (Bitfield-Mask: 0x01)                          */
#define PWRSEQ_LPPWST_RESET_SHIFT           (17UL)                    /*!< RESET (Bit 17)                                        */
#define PWRSEQ_LPPWST_RESET_MASK            (0x20000UL)               /*!< RESET (Bitfield-Mask: 0x01)                           */
/* ========================================================  LPPWEN  ========================================================= */
#define PWRSEQ_LPPWEN_AINCOMP0_SHIFT        (4UL)                     /*!< AINCOMP0 (Bit 4)                                      */
#define PWRSEQ_LPPWEN_AINCOMP0_MASK         (0x10UL)                  /*!< AINCOMP0 (Bitfield-Mask: 0x01)                        */
#define PWRSEQ_LPPWEN_WDT0_SHIFT            (8UL)                     /*!< WDT0 (Bit 8)                                          */
#define PWRSEQ_LPPWEN_WDT0_MASK             (0x100UL)                 /*!< WDT0 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_WDT1_SHIFT            (9UL)                     /*!< WDT1 (Bit 9)                                          */
#define PWRSEQ_LPPWEN_WDT1_MASK             (0x200UL)                 /*!< WDT1 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_CPU1_SHIFT            (10UL)                    /*!< CPU1 (Bit 10)                                         */
#define PWRSEQ_LPPWEN_CPU1_MASK             (0x400UL)                 /*!< CPU1 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR0_SHIFT            (11UL)                    /*!< TMR0 (Bit 11)                                         */
#define PWRSEQ_LPPWEN_TMR0_MASK             (0x800UL)                 /*!< TMR0 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR1_SHIFT            (12UL)                    /*!< TMR1 (Bit 12)                                         */
#define PWRSEQ_LPPWEN_TMR1_MASK             (0x1000UL)                /*!< TMR1 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR2_SHIFT            (13UL)                    /*!< TMR2 (Bit 13)                                         */
#define PWRSEQ_LPPWEN_TMR2_MASK             (0x2000UL)                /*!< TMR2 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR3_SHIFT            (14UL)                    /*!< TMR3 (Bit 14)                                         */
#define PWRSEQ_LPPWEN_TMR3_MASK             (0x4000UL)                /*!< TMR3 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR4_SHIFT            (15UL)                    /*!< TMR4 (Bit 15)                                         */
#define PWRSEQ_LPPWEN_TMR4_MASK             (0x8000UL)                /*!< TMR4 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_TMR5_SHIFT            (16UL)                    /*!< TMR5 (Bit 16)                                         */
#define PWRSEQ_LPPWEN_TMR5_MASK             (0x10000UL)               /*!< TMR5 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_UART0_SHIFT           (17UL)                    /*!< UART0 (Bit 17)                                        */
#define PWRSEQ_LPPWEN_UART0_MASK            (0x20000UL)               /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define PWRSEQ_LPPWEN_UART1_SHIFT           (18UL)                    /*!< UART1 (Bit 18)                                        */
#define PWRSEQ_LPPWEN_UART1_MASK            (0x40000UL)               /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define PWRSEQ_LPPWEN_UART2_SHIFT           (19UL)                    /*!< UART2 (Bit 19)                                        */
#define PWRSEQ_LPPWEN_UART2_MASK            (0x80000UL)               /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define PWRSEQ_LPPWEN_UART3_SHIFT           (20UL)                    /*!< UART3 (Bit 20)                                        */
#define PWRSEQ_LPPWEN_UART3_MASK            (0x100000UL)              /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define PWRSEQ_LPPWEN_I2C0_SHIFT            (21UL)                    /*!< I2C0 (Bit 21)                                         */
#define PWRSEQ_LPPWEN_I2C0_MASK             (0x200000UL)              /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_I2C1_SHIFT            (22UL)                    /*!< I2C1 (Bit 22)                                         */
#define PWRSEQ_LPPWEN_I2C1_MASK             (0x400000UL)              /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_I2C2_SHIFT            (23UL)                    /*!< I2C2 (Bit 23)                                         */
#define PWRSEQ_LPPWEN_I2C2_MASK             (0x800000UL)              /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_I2S_SHIFT             (24UL)                    /*!< I2S (Bit 24)                                          */
#define PWRSEQ_LPPWEN_I2S_MASK              (0x1000000UL)             /*!< I2S (Bitfield-Mask: 0x01)                             */
#define PWRSEQ_LPPWEN_SPI1_SHIFT            (25UL)                    /*!< SPI1 (Bit 25)                                         */
#define PWRSEQ_LPPWEN_SPI1_MASK             (0x2000000UL)             /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define PWRSEQ_LPPWEN_LPCMP_SHIFT           (26UL)                    /*!< LPCMP (Bit 26)                                        */
#define PWRSEQ_LPPWEN_LPCMP_MASK            (0x4000000UL)             /*!< LPCMP (Bitfield-Mask: 0x01)                           */
/* ==========================================================  GP0  ========================================================== */
/* ==========================================================  GP1  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           LPCMP                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define LPCMP_CTRL_EN_SHIFT                 (0UL)                     /*!< EN (Bit 0)                                            */
#define LPCMP_CTRL_EN_MASK                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define LPCMP_CTRL_POL_SHIFT                (5UL)                     /*!< POL (Bit 5)                                           */
#define LPCMP_CTRL_POL_MASK                 (0x20UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define LPCMP_CTRL_INT_EN_SHIFT             (6UL)                     /*!< INT_EN (Bit 6)                                        */
#define LPCMP_CTRL_INT_EN_MASK              (0x40UL)                  /*!< INT_EN (Bitfield-Mask: 0x01)                          */
#define LPCMP_CTRL_OUT_SHIFT                (14UL)                    /*!< OUT (Bit 14)                                          */
#define LPCMP_CTRL_OUT_MASK                 (0x4000UL)                /*!< OUT (Bitfield-Mask: 0x01)                             */
#define LPCMP_CTRL_INT_FL_SHIFT             (15UL)                    /*!< INT_FL (Bit 15)                                       */
#define LPCMP_CTRL_INT_FL_MASK              (0x8000UL)                /*!< INT_FL (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SEC  ========================================================== */
#define RTC_SEC_SEC_SHIFT                   (0UL)                     /*!< SEC (Bit 0)                                           */
#define RTC_SEC_SEC_MASK                    (0xffffffffUL)            /*!< SEC (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  SSEC  ========================================================== */
#define RTC_SSEC_SSEC_SHIFT                 (0UL)                     /*!< SSEC (Bit 0)                                          */
#define RTC_SSEC_SSEC_MASK                  (0xfffUL)                 /*!< SSEC (Bitfield-Mask: 0xfff)                           */
/* =========================================================  TODA  ========================================================== */
#define RTC_TODA_TOD_ALARM_SHIFT            (0UL)                     /*!< TOD_ALARM (Bit 0)                                     */
#define RTC_TODA_TOD_ALARM_MASK             (0xfffffUL)               /*!< TOD_ALARM (Bitfield-Mask: 0xfffff)                    */
/* =========================================================  SSECA  ========================================================= */
#define RTC_SSECA_SSEC_ALARM_SHIFT          (0UL)                     /*!< SSEC_ALARM (Bit 0)                                    */
#define RTC_SSECA_SSEC_ALARM_MASK           (0xffffffffUL)            /*!< SSEC_ALARM (Bitfield-Mask: 0xffffffff)                */
/* =========================================================  CTRL  ========================================================== */
#define RTC_CTRL_EN_SHIFT                   (0UL)                     /*!< EN (Bit 0)                                            */
#define RTC_CTRL_EN_MASK                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define RTC_CTRL_TOD_ALARM_IE_SHIFT         (1UL)                     /*!< TOD_ALARM_IE (Bit 1)                                  */
#define RTC_CTRL_TOD_ALARM_IE_MASK          (0x2UL)                   /*!< TOD_ALARM_IE (Bitfield-Mask: 0x01)                    */
#define RTC_CTRL_SSEC_ALARM_IE_SHIFT        (2UL)                     /*!< SSEC_ALARM_IE (Bit 2)                                 */
#define RTC_CTRL_SSEC_ALARM_IE_MASK         (0x4UL)                   /*!< SSEC_ALARM_IE (Bitfield-Mask: 0x01)                   */
#define RTC_CTRL_BUSY_SHIFT                 (3UL)                     /*!< BUSY (Bit 3)                                          */
#define RTC_CTRL_BUSY_MASK                  (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define RTC_CTRL_RDY_SHIFT                  (4UL)                     /*!< RDY (Bit 4)                                           */
#define RTC_CTRL_RDY_MASK                   (0x10UL)                  /*!< RDY (Bitfield-Mask: 0x01)                             */
#define RTC_CTRL_RDY_IE_SHIFT               (5UL)                     /*!< RDY_IE (Bit 5)                                        */
#define RTC_CTRL_RDY_IE_MASK                (0x20UL)                  /*!< RDY_IE (Bitfield-Mask: 0x01)                          */
#define RTC_CTRL_TOD_ALARM_SHIFT            (6UL)                     /*!< TOD_ALARM (Bit 6)                                     */
#define RTC_CTRL_TOD_ALARM_MASK             (0x40UL)                  /*!< TOD_ALARM (Bitfield-Mask: 0x01)                       */
#define RTC_CTRL_SSEC_ALARM_SHIFT           (7UL)                     /*!< SSEC_ALARM (Bit 7)                                    */
#define RTC_CTRL_SSEC_ALARM_MASK            (0x80UL)                  /*!< SSEC_ALARM (Bitfield-Mask: 0x01)                      */
#define RTC_CTRL_SQW_EN_SHIFT               (8UL)                     /*!< SQW_EN (Bit 8)                                        */
#define RTC_CTRL_SQW_EN_MASK                (0x100UL)                 /*!< SQW_EN (Bitfield-Mask: 0x01)                          */
#define RTC_CTRL_SQW_SEL_SHIFT              (9UL)                     /*!< SQW_SEL (Bit 9)                                       */
#define RTC_CTRL_SQW_SEL_MASK               (0x600UL)                 /*!< SQW_SEL (Bitfield-Mask: 0x03)                         */
#define RTC_CTRL_RD_EN_SHIFT                (14UL)                    /*!< RD_EN (Bit 14)                                        */
#define RTC_CTRL_RD_EN_MASK                 (0x4000UL)                /*!< RD_EN (Bitfield-Mask: 0x01)                           */
#define RTC_CTRL_WR_EN_SHIFT                (15UL)                    /*!< WR_EN (Bit 15)                                        */
#define RTC_CTRL_WR_EN_MASK                 (0x8000UL)                /*!< WR_EN (Bitfield-Mask: 0x01)                           */
/* =========================================================  TRIM  ========================================================== */
#define RTC_TRIM_TRIM_SHIFT                 (0UL)                     /*!< TRIM (Bit 0)                                          */
#define RTC_TRIM_TRIM_MASK                  (0xffUL)                  /*!< TRIM (Bitfield-Mask: 0xff)                            */
#define RTC_TRIM_VRTC_TMR_SHIFT             (8UL)                     /*!< VRTC_TMR (Bit 8)                                      */
#define RTC_TRIM_VRTC_TMR_MASK              (0xffffff00UL)            /*!< VRTC_TMR (Bitfield-Mask: 0xffffff)                    */
/* ========================================================  OSCCTRL  ======================================================== */
#define RTC_OSCCTRL_BYPASS_SHIFT            (4UL)                     /*!< BYPASS (Bit 4)                                        */
#define RTC_OSCCTRL_BYPASS_MASK             (0x10UL)                  /*!< BYPASS (Bitfield-Mask: 0x01)                          */
#define RTC_OSCCTRL_SQW_32K_SHIFT           (5UL)                     /*!< SQW_32K (Bit 5)                                       */
#define RTC_OSCCTRL_SQW_32K_MASK            (0x20UL)                  /*!< SQW_32K (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  FIFO32  ========================================================= */
#define SPI0_FIFO32_DATA_SHIFT              (0UL)                     /*!< DATA (Bit 0)                                          */
#define SPI0_FIFO32_DATA_MASK               (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  FIFO16  ========================================================= */
#define SPI0_FIFO16_DATA_SHIFT              (0UL)                     /*!< DATA (Bit 0)                                          */
#define SPI0_FIFO16_DATA_MASK               (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  FIFO8  ========================================================= */
#define SPI0_FIFO8_DATA_SHIFT               (0UL)                     /*!< DATA (Bit 0)                                          */
#define SPI0_FIFO8_DATA_MASK                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  CTRL0  ========================================================= */
#define SPI0_CTRL0_EN_SHIFT                 (0UL)                     /*!< EN (Bit 0)                                            */
#define SPI0_CTRL0_EN_MASK                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define SPI0_CTRL0_MST_MODE_SHIFT           (1UL)                     /*!< MST_MODE (Bit 1)                                      */
#define SPI0_CTRL0_MST_MODE_MASK            (0x2UL)                   /*!< MST_MODE (Bitfield-Mask: 0x01)                        */
#define SPI0_CTRL0_SS_IO_SHIFT              (4UL)                     /*!< SS_IO (Bit 4)                                         */
#define SPI0_CTRL0_SS_IO_MASK               (0x10UL)                  /*!< SS_IO (Bitfield-Mask: 0x01)                           */
#define SPI0_CTRL0_START_SHIFT              (5UL)                     /*!< START (Bit 5)                                         */
#define SPI0_CTRL0_START_MASK               (0x20UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define SPI0_CTRL0_SS_CTRL_SHIFT            (8UL)                     /*!< SS_CTRL (Bit 8)                                       */
#define SPI0_CTRL0_SS_CTRL_MASK             (0x100UL)                 /*!< SS_CTRL (Bitfield-Mask: 0x01)                         */
#define SPI0_CTRL0_SS_ACTIVE_SHIFT          (16UL)                    /*!< SS_ACTIVE (Bit 16)                                    */
#define SPI0_CTRL0_SS_ACTIVE_MASK           (0xf0000UL)               /*!< SS_ACTIVE (Bitfield-Mask: 0x0f)                       */
/* =========================================================  CTRL1  ========================================================= */
#define SPI0_CTRL1_TX_NUM_CHAR_SHIFT        (0UL)                     /*!< TX_NUM_CHAR (Bit 0)                                   */
#define SPI0_CTRL1_TX_NUM_CHAR_MASK         (0xffffUL)                /*!< TX_NUM_CHAR (Bitfield-Mask: 0xffff)                   */
#define SPI0_CTRL1_RX_NUM_CHAR_SHIFT        (16UL)                    /*!< RX_NUM_CHAR (Bit 16)                                  */
#define SPI0_CTRL1_RX_NUM_CHAR_MASK         (0xffff0000UL)            /*!< RX_NUM_CHAR (Bitfield-Mask: 0xffff)                   */
/* =========================================================  CTRL2  ========================================================= */
#define SPI0_CTRL2_CLKPHA_SHIFT             (0UL)                     /*!< CLKPHA (Bit 0)                                        */
#define SPI0_CTRL2_CLKPHA_MASK              (0x1UL)                   /*!< CLKPHA (Bitfield-Mask: 0x01)                          */
#define SPI0_CTRL2_CLKPOL_SHIFT             (1UL)                     /*!< CLKPOL (Bit 1)                                        */
#define SPI0_CTRL2_CLKPOL_MASK              (0x2UL)                   /*!< CLKPOL (Bitfield-Mask: 0x01)                          */
#define SPI0_CTRL2_NUMBITS_SHIFT            (8UL)                     /*!< NUMBITS (Bit 8)                                       */
#define SPI0_CTRL2_NUMBITS_MASK             (0xf00UL)                 /*!< NUMBITS (Bitfield-Mask: 0x0f)                         */
#define SPI0_CTRL2_DATA_WIDTH_SHIFT         (12UL)                    /*!< DATA_WIDTH (Bit 12)                                   */
#define SPI0_CTRL2_DATA_WIDTH_MASK          (0x3000UL)                /*!< DATA_WIDTH (Bitfield-Mask: 0x03)                      */
#define SPI0_CTRL2_THREE_WIRE_SHIFT         (15UL)                    /*!< THREE_WIRE (Bit 15)                                   */
#define SPI0_CTRL2_THREE_WIRE_MASK          (0x8000UL)                /*!< THREE_WIRE (Bitfield-Mask: 0x01)                      */
#define SPI0_CTRL2_SS_POL_SHIFT             (16UL)                    /*!< SS_POL (Bit 16)                                       */
#define SPI0_CTRL2_SS_POL_MASK              (0xff0000UL)              /*!< SS_POL (Bitfield-Mask: 0xff)                          */
/* ========================================================  SSTIME  ========================================================= */
#define SPI0_SSTIME_PRE_SHIFT               (0UL)                     /*!< PRE (Bit 0)                                           */
#define SPI0_SSTIME_PRE_MASK                (0xffUL)                  /*!< PRE (Bitfield-Mask: 0xff)                             */
#define SPI0_SSTIME_POST_SHIFT              (8UL)                     /*!< POST (Bit 8)                                          */
#define SPI0_SSTIME_POST_MASK               (0xff00UL)                /*!< POST (Bitfield-Mask: 0xff)                            */
#define SPI0_SSTIME_INACT_SHIFT             (16UL)                    /*!< INACT (Bit 16)                                        */
#define SPI0_SSTIME_INACT_MASK              (0xff0000UL)              /*!< INACT (Bitfield-Mask: 0xff)                           */
/* ========================================================  CLKCTRL  ======================================================== */
#define SPI0_CLKCTRL_LO_SHIFT               (0UL)                     /*!< LO (Bit 0)                                            */
#define SPI0_CLKCTRL_LO_MASK                (0xffUL)                  /*!< LO (Bitfield-Mask: 0xff)                              */
#define SPI0_CLKCTRL_HI_SHIFT               (8UL)                     /*!< HI (Bit 8)                                            */
#define SPI0_CLKCTRL_HI_MASK                (0xff00UL)                /*!< HI (Bitfield-Mask: 0xff)                              */
#define SPI0_CLKCTRL_CLKDIV_SHIFT           (16UL)                    /*!< CLKDIV (Bit 16)                                       */
#define SPI0_CLKCTRL_CLKDIV_MASK            (0xf0000UL)               /*!< CLKDIV (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  DMA  ========================================================== */
#define SPI0_DMA_TX_THD_VAL_SHIFT           (0UL)                     /*!< TX_THD_VAL (Bit 0)                                    */
#define SPI0_DMA_TX_THD_VAL_MASK            (0x1fUL)                  /*!< TX_THD_VAL (Bitfield-Mask: 0x1f)                      */
#define SPI0_DMA_TX_FIFO_EN_SHIFT           (6UL)                     /*!< TX_FIFO_EN (Bit 6)                                    */
#define SPI0_DMA_TX_FIFO_EN_MASK            (0x40UL)                  /*!< TX_FIFO_EN (Bitfield-Mask: 0x01)                      */
#define SPI0_DMA_TX_FLUSH_SHIFT             (7UL)                     /*!< TX_FLUSH (Bit 7)                                      */
#define SPI0_DMA_TX_FLUSH_MASK              (0x80UL)                  /*!< TX_FLUSH (Bitfield-Mask: 0x01)                        */
#define SPI0_DMA_TX_LVL_SHIFT               (8UL)                     /*!< TX_LVL (Bit 8)                                        */
#define SPI0_DMA_TX_LVL_MASK                (0x3f00UL)                /*!< TX_LVL (Bitfield-Mask: 0x3f)                          */
#define SPI0_DMA_DMA_TX_EN_SHIFT            (15UL)                    /*!< DMA_TX_EN (Bit 15)                                    */
#define SPI0_DMA_DMA_TX_EN_MASK             (0x8000UL)                /*!< DMA_TX_EN (Bitfield-Mask: 0x01)                       */
#define SPI0_DMA_RX_THD_VAL_SHIFT           (16UL)                    /*!< RX_THD_VAL (Bit 16)                                   */
#define SPI0_DMA_RX_THD_VAL_MASK            (0x1f0000UL)              /*!< RX_THD_VAL (Bitfield-Mask: 0x1f)                      */
#define SPI0_DMA_RX_FIFO_EN_SHIFT           (22UL)                    /*!< RX_FIFO_EN (Bit 22)                                   */
#define SPI0_DMA_RX_FIFO_EN_MASK            (0x400000UL)              /*!< RX_FIFO_EN (Bitfield-Mask: 0x01)                      */
#define SPI0_DMA_RX_FLUSH_SHIFT             (23UL)                    /*!< RX_FLUSH (Bit 23)                                     */
#define SPI0_DMA_RX_FLUSH_MASK              (0x800000UL)              /*!< RX_FLUSH (Bitfield-Mask: 0x01)                        */
#define SPI0_DMA_RX_LVL_SHIFT               (24UL)                    /*!< RX_LVL (Bit 24)                                       */
#define SPI0_DMA_RX_LVL_MASK                (0x3f000000UL)            /*!< RX_LVL (Bitfield-Mask: 0x3f)                          */
#define SPI0_DMA_DMA_RX_EN_SHIFT            (31UL)                    /*!< DMA_RX_EN (Bit 31)                                    */
#define SPI0_DMA_DMA_RX_EN_MASK             (0x80000000UL)            /*!< DMA_RX_EN (Bitfield-Mask: 0x01)                       */
/* =========================================================  INTFL  ========================================================= */
#define SPI0_INTFL_TX_THD_SHIFT             (0UL)                     /*!< TX_THD (Bit 0)                                        */
#define SPI0_INTFL_TX_THD_MASK              (0x1UL)                   /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_INTFL_TX_EM_SHIFT              (1UL)                     /*!< TX_EM (Bit 1)                                         */
#define SPI0_INTFL_TX_EM_MASK               (0x2UL)                   /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_RX_THD_SHIFT             (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define SPI0_INTFL_RX_THD_MASK              (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_INTFL_RX_FULL_SHIFT            (3UL)                     /*!< RX_FULL (Bit 3)                                       */
#define SPI0_INTFL_RX_FULL_MASK             (0x8UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define SPI0_INTFL_SSA_SHIFT                (4UL)                     /*!< SSA (Bit 4)                                           */
#define SPI0_INTFL_SSA_MASK                 (0x10UL)                  /*!< SSA (Bitfield-Mask: 0x01)                             */
#define SPI0_INTFL_SSD_SHIFT                (5UL)                     /*!< SSD (Bit 5)                                           */
#define SPI0_INTFL_SSD_MASK                 (0x20UL)                  /*!< SSD (Bitfield-Mask: 0x01)                             */
#define SPI0_INTFL_FAULT_SHIFT              (8UL)                     /*!< FAULT (Bit 8)                                         */
#define SPI0_INTFL_FAULT_MASK               (0x100UL)                 /*!< FAULT (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_ABORT_SHIFT              (9UL)                     /*!< ABORT (Bit 9)                                         */
#define SPI0_INTFL_ABORT_MASK               (0x200UL)                 /*!< ABORT (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_MST_DONE_SHIFT           (11UL)                    /*!< MST_DONE (Bit 11)                                     */
#define SPI0_INTFL_MST_DONE_MASK            (0x800UL)                 /*!< MST_DONE (Bitfield-Mask: 0x01)                        */
#define SPI0_INTFL_TX_OV_SHIFT              (12UL)                    /*!< TX_OV (Bit 12)                                        */
#define SPI0_INTFL_TX_OV_MASK               (0x1000UL)                /*!< TX_OV (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_TX_UN_SHIFT              (13UL)                    /*!< TX_UN (Bit 13)                                        */
#define SPI0_INTFL_TX_UN_MASK               (0x2000UL)                /*!< TX_UN (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_RX_OV_SHIFT              (14UL)                    /*!< RX_OV (Bit 14)                                        */
#define SPI0_INTFL_RX_OV_MASK               (0x4000UL)                /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define SPI0_INTFL_RX_UN_SHIFT              (15UL)                    /*!< RX_UN (Bit 15)                                        */
#define SPI0_INTFL_RX_UN_MASK               (0x8000UL)                /*!< RX_UN (Bitfield-Mask: 0x01)                           */
/* =========================================================  INTEN  ========================================================= */
#define SPI0_INTEN_TX_THD_SHIFT             (0UL)                     /*!< TX_THD (Bit 0)                                        */
#define SPI0_INTEN_TX_THD_MASK              (0x1UL)                   /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_INTEN_TX_EM_SHIFT              (1UL)                     /*!< TX_EM (Bit 1)                                         */
#define SPI0_INTEN_TX_EM_MASK               (0x2UL)                   /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_RX_THD_SHIFT             (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define SPI0_INTEN_RX_THD_MASK              (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_INTEN_RX_FULL_SHIFT            (3UL)                     /*!< RX_FULL (Bit 3)                                       */
#define SPI0_INTEN_RX_FULL_MASK             (0x8UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define SPI0_INTEN_SSA_SHIFT                (4UL)                     /*!< SSA (Bit 4)                                           */
#define SPI0_INTEN_SSA_MASK                 (0x10UL)                  /*!< SSA (Bitfield-Mask: 0x01)                             */
#define SPI0_INTEN_SSD_SHIFT                (5UL)                     /*!< SSD (Bit 5)                                           */
#define SPI0_INTEN_SSD_MASK                 (0x20UL)                  /*!< SSD (Bitfield-Mask: 0x01)                             */
#define SPI0_INTEN_FAULT_SHIFT              (8UL)                     /*!< FAULT (Bit 8)                                         */
#define SPI0_INTEN_FAULT_MASK               (0x100UL)                 /*!< FAULT (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_ABORT_SHIFT              (9UL)                     /*!< ABORT (Bit 9)                                         */
#define SPI0_INTEN_ABORT_MASK               (0x200UL)                 /*!< ABORT (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_MST_DONE_SHIFT           (11UL)                    /*!< MST_DONE (Bit 11)                                     */
#define SPI0_INTEN_MST_DONE_MASK            (0x800UL)                 /*!< MST_DONE (Bitfield-Mask: 0x01)                        */
#define SPI0_INTEN_TX_OV_SHIFT              (12UL)                    /*!< TX_OV (Bit 12)                                        */
#define SPI0_INTEN_TX_OV_MASK               (0x1000UL)                /*!< TX_OV (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_TX_UN_SHIFT              (13UL)                    /*!< TX_UN (Bit 13)                                        */
#define SPI0_INTEN_TX_UN_MASK               (0x2000UL)                /*!< TX_UN (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_RX_OV_SHIFT              (14UL)                    /*!< RX_OV (Bit 14)                                        */
#define SPI0_INTEN_RX_OV_MASK               (0x4000UL)                /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define SPI0_INTEN_RX_UN_SHIFT              (15UL)                    /*!< RX_UN (Bit 15)                                        */
#define SPI0_INTEN_RX_UN_MASK               (0x8000UL)                /*!< RX_UN (Bitfield-Mask: 0x01)                           */
/* =========================================================  WKFL  ========================================================== */
#define SPI0_WKFL_TX_THD_SHIFT              (0UL)                     /*!< TX_THD (Bit 0)                                        */
#define SPI0_WKFL_TX_THD_MASK               (0x1UL)                   /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_WKFL_TX_EM_SHIFT               (1UL)                     /*!< TX_EM (Bit 1)                                         */
#define SPI0_WKFL_TX_EM_MASK                (0x2UL)                   /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define SPI0_WKFL_RX_THD_SHIFT              (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define SPI0_WKFL_RX_THD_MASK               (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_WKFL_RX_FULL_SHIFT             (3UL)                     /*!< RX_FULL (Bit 3)                                       */
#define SPI0_WKFL_RX_FULL_MASK              (0x8UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
/* =========================================================  WKEN  ========================================================== */
#define SPI0_WKEN_TX_THD_SHIFT              (0UL)                     /*!< TX_THD (Bit 0)                                        */
#define SPI0_WKEN_TX_THD_MASK               (0x1UL)                   /*!< TX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_WKEN_TX_EM_SHIFT               (1UL)                     /*!< TX_EM (Bit 1)                                         */
#define SPI0_WKEN_TX_EM_MASK                (0x2UL)                   /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define SPI0_WKEN_RX_THD_SHIFT              (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define SPI0_WKEN_RX_THD_MASK               (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define SPI0_WKEN_RX_FULL_SHIFT             (3UL)                     /*!< RX_FULL (Bit 3)                                       */
#define SPI0_WKEN_RX_FULL_MASK              (0x8UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
/* =========================================================  STAT  ========================================================== */
#define SPI0_STAT_BUSY_SHIFT                (0UL)                     /*!< BUSY (Bit 0)                                          */
#define SPI0_STAT_BUSY_MASK                 (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            TMR                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
#define TMR_CNT_COUNT_SHIFT                 (0UL)                     /*!< COUNT (Bit 0)                                         */
#define TMR_CNT_COUNT_MASK                  (0xffffffffUL)            /*!< COUNT (Bitfield-Mask: 0xffffffff)                     */
/* ==========================================================  CMP  ========================================================== */
#define TMR_CMP_COMPARE_SHIFT               (0UL)                     /*!< COMPARE (Bit 0)                                       */
#define TMR_CMP_COMPARE_MASK                (0xffffffffUL)            /*!< COMPARE (Bitfield-Mask: 0xffffffff)                   */
/* ==========================================================  PWM  ========================================================== */
#define TMR_PWM_PWM_SHIFT                   (0UL)                     /*!< PWM (Bit 0)                                           */
#define TMR_PWM_PWM_MASK                    (0xffffffffUL)            /*!< PWM (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  INTFL  ========================================================= */
#define TMR_INTFL_IRQ_A_SHIFT               (0UL)                     /*!< IRQ_A (Bit 0)                                         */
#define TMR_INTFL_IRQ_A_MASK                (0x1UL)                   /*!< IRQ_A (Bitfield-Mask: 0x01)                           */
#define TMR_INTFL_WRDONE_A_SHIFT            (8UL)                     /*!< WRDONE_A (Bit 8)                                      */
#define TMR_INTFL_WRDONE_A_MASK             (0x100UL)                 /*!< WRDONE_A (Bitfield-Mask: 0x01)                        */
#define TMR_INTFL_WR_DIS_A_SHIFT            (9UL)                     /*!< WR_DIS_A (Bit 9)                                      */
#define TMR_INTFL_WR_DIS_A_MASK             (0x200UL)                 /*!< WR_DIS_A (Bitfield-Mask: 0x01)                        */
#define TMR_INTFL_IRQ_B_SHIFT               (16UL)                    /*!< IRQ_B (Bit 16)                                        */
#define TMR_INTFL_IRQ_B_MASK                (0x10000UL)               /*!< IRQ_B (Bitfield-Mask: 0x01)                           */
#define TMR_INTFL_WRDONE_B_SHIFT            (24UL)                    /*!< WRDONE_B (Bit 24)                                     */
#define TMR_INTFL_WRDONE_B_MASK             (0x1000000UL)             /*!< WRDONE_B (Bitfield-Mask: 0x01)                        */
#define TMR_INTFL_WR_DIS_B_SHIFT            (25UL)                    /*!< WR_DIS_B (Bit 25)                                     */
#define TMR_INTFL_WR_DIS_B_MASK             (0x2000000UL)             /*!< WR_DIS_B (Bitfield-Mask: 0x01)                        */
/* =========================================================  CTRL0  ========================================================= */
#define TMR_CTRL0_MODE_A_SHIFT              (0UL)                     /*!< MODE_A (Bit 0)                                        */
#define TMR_CTRL0_MODE_A_MASK               (0xfUL)                   /*!< MODE_A (Bitfield-Mask: 0x0f)                          */
#define TMR_CTRL0_CLKDIV_A_SHIFT            (4UL)                     /*!< CLKDIV_A (Bit 4)                                      */
#define TMR_CTRL0_CLKDIV_A_MASK             (0xf0UL)                  /*!< CLKDIV_A (Bitfield-Mask: 0x0f)                        */
#define TMR_CTRL0_POL_A_SHIFT               (8UL)                     /*!< POL_A (Bit 8)                                         */
#define TMR_CTRL0_POL_A_MASK                (0x100UL)                 /*!< POL_A (Bitfield-Mask: 0x01)                           */
#define TMR_CTRL0_PWMSYNC_A_SHIFT           (9UL)                     /*!< PWMSYNC_A (Bit 9)                                     */
#define TMR_CTRL0_PWMSYNC_A_MASK            (0x200UL)                 /*!< PWMSYNC_A (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_NOLHPOL_A_SHIFT           (10UL)                    /*!< NOLHPOL_A (Bit 10)                                    */
#define TMR_CTRL0_NOLHPOL_A_MASK            (0x400UL)                 /*!< NOLHPOL_A (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_NOLLPOL_A_SHIFT           (11UL)                    /*!< NOLLPOL_A (Bit 11)                                    */
#define TMR_CTRL0_NOLLPOL_A_MASK            (0x800UL)                 /*!< NOLLPOL_A (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_PWMCKBD_A_SHIFT           (12UL)                    /*!< PWMCKBD_A (Bit 12)                                    */
#define TMR_CTRL0_PWMCKBD_A_MASK            (0x1000UL)                /*!< PWMCKBD_A (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_RST_A_SHIFT               (13UL)                    /*!< RST_A (Bit 13)                                        */
#define TMR_CTRL0_RST_A_MASK                (0x2000UL)                /*!< RST_A (Bitfield-Mask: 0x01)                           */
#define TMR_CTRL0_CLKEN_A_SHIFT             (14UL)                    /*!< CLKEN_A (Bit 14)                                      */
#define TMR_CTRL0_CLKEN_A_MASK              (0x4000UL)                /*!< CLKEN_A (Bitfield-Mask: 0x01)                         */
#define TMR_CTRL0_EN_A_SHIFT                (15UL)                    /*!< EN_A (Bit 15)                                         */
#define TMR_CTRL0_EN_A_MASK                 (0x8000UL)                /*!< EN_A (Bitfield-Mask: 0x01)                            */
#define TMR_CTRL0_MODE_B_SHIFT              (16UL)                    /*!< MODE_B (Bit 16)                                       */
#define TMR_CTRL0_MODE_B_MASK               (0xf0000UL)               /*!< MODE_B (Bitfield-Mask: 0x0f)                          */
#define TMR_CTRL0_CLKDIV_B_SHIFT            (20UL)                    /*!< CLKDIV_B (Bit 20)                                     */
#define TMR_CTRL0_CLKDIV_B_MASK             (0xf00000UL)              /*!< CLKDIV_B (Bitfield-Mask: 0x0f)                        */
#define TMR_CTRL0_POL_B_SHIFT               (24UL)                    /*!< POL_B (Bit 24)                                        */
#define TMR_CTRL0_POL_B_MASK                (0x1000000UL)             /*!< POL_B (Bitfield-Mask: 0x01)                           */
#define TMR_CTRL0_PWMSYNC_B_SHIFT           (25UL)                    /*!< PWMSYNC_B (Bit 25)                                    */
#define TMR_CTRL0_PWMSYNC_B_MASK            (0x2000000UL)             /*!< PWMSYNC_B (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_NOLHPOL_B_SHIFT           (26UL)                    /*!< NOLHPOL_B (Bit 26)                                    */
#define TMR_CTRL0_NOLHPOL_B_MASK            (0x4000000UL)             /*!< NOLHPOL_B (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_NOLLPOL_B_SHIFT           (27UL)                    /*!< NOLLPOL_B (Bit 27)                                    */
#define TMR_CTRL0_NOLLPOL_B_MASK            (0x8000000UL)             /*!< NOLLPOL_B (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_PWMCKBD_B_SHIFT           (28UL)                    /*!< PWMCKBD_B (Bit 28)                                    */
#define TMR_CTRL0_PWMCKBD_B_MASK            (0x10000000UL)            /*!< PWMCKBD_B (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL0_RST_B_SHIFT               (29UL)                    /*!< RST_B (Bit 29)                                        */
#define TMR_CTRL0_RST_B_MASK                (0x20000000UL)            /*!< RST_B (Bitfield-Mask: 0x01)                           */
#define TMR_CTRL0_CLKEN_B_SHIFT             (30UL)                    /*!< CLKEN_B (Bit 30)                                      */
#define TMR_CTRL0_CLKEN_B_MASK              (0x40000000UL)            /*!< CLKEN_B (Bitfield-Mask: 0x01)                         */
#define TMR_CTRL0_EN_B_SHIFT                (31UL)                    /*!< EN_B (Bit 31)                                         */
#define TMR_CTRL0_EN_B_MASK                 (0x80000000UL)            /*!< EN_B (Bitfield-Mask: 0x01)                            */
/* ========================================================  NOLCMP  ========================================================= */
#define TMR_NOLCMP_LO_A_SHIFT               (0UL)                     /*!< LO_A (Bit 0)                                          */
#define TMR_NOLCMP_LO_A_MASK                (0xffUL)                  /*!< LO_A (Bitfield-Mask: 0xff)                            */
#define TMR_NOLCMP_HI_A_SHIFT               (8UL)                     /*!< HI_A (Bit 8)                                          */
#define TMR_NOLCMP_HI_A_MASK                (0xff00UL)                /*!< HI_A (Bitfield-Mask: 0xff)                            */
#define TMR_NOLCMP_LO_B_SHIFT               (16UL)                    /*!< LO_B (Bit 16)                                         */
#define TMR_NOLCMP_LO_B_MASK                (0xff0000UL)              /*!< LO_B (Bitfield-Mask: 0xff)                            */
#define TMR_NOLCMP_HI_B_SHIFT               (24UL)                    /*!< HI_B (Bit 24)                                         */
#define TMR_NOLCMP_HI_B_MASK                (0xff000000UL)            /*!< HI_B (Bitfield-Mask: 0xff)                            */
/* =========================================================  CTRL1  ========================================================= */
#define TMR_CTRL1_CLKSEL_A_SHIFT            (0UL)                     /*!< CLKSEL_A (Bit 0)                                      */
#define TMR_CTRL1_CLKSEL_A_MASK             (0x3UL)                   /*!< CLKSEL_A (Bitfield-Mask: 0x03)                        */
#define TMR_CTRL1_CLKEN_A_SHIFT             (2UL)                     /*!< CLKEN_A (Bit 2)                                       */
#define TMR_CTRL1_CLKEN_A_MASK              (0x4UL)                   /*!< CLKEN_A (Bitfield-Mask: 0x01)                         */
#define TMR_CTRL1_CLKRDY_A_SHIFT            (3UL)                     /*!< CLKRDY_A (Bit 3)                                      */
#define TMR_CTRL1_CLKRDY_A_MASK             (0x8UL)                   /*!< CLKRDY_A (Bitfield-Mask: 0x01)                        */
#define TMR_CTRL1_EVENT_SEL_A_SHIFT         (4UL)                     /*!< EVENT_SEL_A (Bit 4)                                   */
#define TMR_CTRL1_EVENT_SEL_A_MASK          (0x70UL)                  /*!< EVENT_SEL_A (Bitfield-Mask: 0x07)                     */
#define TMR_CTRL1_NEGTRIG_A_SHIFT           (7UL)                     /*!< NEGTRIG_A (Bit 7)                                     */
#define TMR_CTRL1_NEGTRIG_A_MASK            (0x80UL)                  /*!< NEGTRIG_A (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL1_IE_A_SHIFT                (8UL)                     /*!< IE_A (Bit 8)                                          */
#define TMR_CTRL1_IE_A_MASK                 (0x100UL)                 /*!< IE_A (Bitfield-Mask: 0x01)                            */
#define TMR_CTRL1_CAPEVENT_SEL_A_SHIFT      (9UL)                     /*!< CAPEVENT_SEL_A (Bit 9)                                */
#define TMR_CTRL1_CAPEVENT_SEL_A_MASK       (0x600UL)                 /*!< CAPEVENT_SEL_A (Bitfield-Mask: 0x03)                  */
#define TMR_CTRL1_SW_CAPEVENT_A_SHIFT       (11UL)                    /*!< SW_CAPEVENT_A (Bit 11)                                */
#define TMR_CTRL1_SW_CAPEVENT_A_MASK        (0x800UL)                 /*!< SW_CAPEVENT_A (Bitfield-Mask: 0x01)                   */
#define TMR_CTRL1_WE_A_SHIFT                (12UL)                    /*!< WE_A (Bit 12)                                         */
#define TMR_CTRL1_WE_A_MASK                 (0x1000UL)                /*!< WE_A (Bitfield-Mask: 0x01)                            */
#define TMR_CTRL1_OUTEN_A_SHIFT             (13UL)                    /*!< OUTEN_A (Bit 13)                                      */
#define TMR_CTRL1_OUTEN_A_MASK              (0x2000UL)                /*!< OUTEN_A (Bitfield-Mask: 0x01)                         */
#define TMR_CTRL1_OUTBEN_A_SHIFT            (14UL)                    /*!< OUTBEN_A (Bit 14)                                     */
#define TMR_CTRL1_OUTBEN_A_MASK             (0x4000UL)                /*!< OUTBEN_A (Bitfield-Mask: 0x01)                        */
#define TMR_CTRL1_CLKSEL_B_SHIFT            (16UL)                    /*!< CLKSEL_B (Bit 16)                                     */
#define TMR_CTRL1_CLKSEL_B_MASK             (0x30000UL)               /*!< CLKSEL_B (Bitfield-Mask: 0x03)                        */
#define TMR_CTRL1_CLKEN_B_SHIFT             (18UL)                    /*!< CLKEN_B (Bit 18)                                      */
#define TMR_CTRL1_CLKEN_B_MASK              (0x40000UL)               /*!< CLKEN_B (Bitfield-Mask: 0x01)                         */
#define TMR_CTRL1_CLKRDY_B_SHIFT            (19UL)                    /*!< CLKRDY_B (Bit 19)                                     */
#define TMR_CTRL1_CLKRDY_B_MASK             (0x80000UL)               /*!< CLKRDY_B (Bitfield-Mask: 0x01)                        */
#define TMR_CTRL1_EVENT_SEL_B_SHIFT         (20UL)                    /*!< EVENT_SEL_B (Bit 20)                                  */
#define TMR_CTRL1_EVENT_SEL_B_MASK          (0x700000UL)              /*!< EVENT_SEL_B (Bitfield-Mask: 0x07)                     */
#define TMR_CTRL1_NEGTRIG_B_SHIFT           (23UL)                    /*!< NEGTRIG_B (Bit 23)                                    */
#define TMR_CTRL1_NEGTRIG_B_MASK            (0x800000UL)              /*!< NEGTRIG_B (Bitfield-Mask: 0x01)                       */
#define TMR_CTRL1_IE_B_SHIFT                (24UL)                    /*!< IE_B (Bit 24)                                         */
#define TMR_CTRL1_IE_B_MASK                 (0x1000000UL)             /*!< IE_B (Bitfield-Mask: 0x01)                            */
#define TMR_CTRL1_CAPEVENT_SEL_B_SHIFT      (25UL)                    /*!< CAPEVENT_SEL_B (Bit 25)                               */
#define TMR_CTRL1_CAPEVENT_SEL_B_MASK       (0x6000000UL)             /*!< CAPEVENT_SEL_B (Bitfield-Mask: 0x03)                  */
#define TMR_CTRL1_SW_CAPEVENT_B_SHIFT       (27UL)                    /*!< SW_CAPEVENT_B (Bit 27)                                */
#define TMR_CTRL1_SW_CAPEVENT_B_MASK        (0x8000000UL)             /*!< SW_CAPEVENT_B (Bitfield-Mask: 0x01)                   */
#define TMR_CTRL1_WE_B_SHIFT                (28UL)                    /*!< WE_B (Bit 28)                                         */
#define TMR_CTRL1_WE_B_MASK                 (0x10000000UL)            /*!< WE_B (Bitfield-Mask: 0x01)                            */
#define TMR_CTRL1_CASCADE_SHIFT             (31UL)                    /*!< CASCADE (Bit 31)                                      */
#define TMR_CTRL1_CASCADE_MASK              (0x80000000UL)            /*!< CASCADE (Bitfield-Mask: 0x01)                         */
/* =========================================================  WKFL  ========================================================== */
#define TMR_WKFL_A_SHIFT                    (0UL)                     /*!< A (Bit 0)                                             */
#define TMR_WKFL_A_MASK                     (0x1UL)                   /*!< A (Bitfield-Mask: 0x01)                               */
#define TMR_WKFL_B_SHIFT                    (16UL)                    /*!< B (Bit 16)                                            */
#define TMR_WKFL_B_MASK                     (0x10000UL)               /*!< B (Bitfield-Mask: 0x01)                               */


/* =========================================================================================================================== */
/* ================                                           TRNG                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define TRNG_CTRL_RND_IE_SHIFT              (1UL)                     /*!< RND_IE (Bit 1)                                        */
#define TRNG_CTRL_RND_IE_MASK               (0x2UL)                   /*!< RND_IE (Bitfield-Mask: 0x01)                          */
#define TRNG_CTRL_KEYGEN_SHIFT              (3UL)                     /*!< KEYGEN (Bit 3)                                        */
#define TRNG_CTRL_KEYGEN_MASK               (0x8UL)                   /*!< KEYGEN (Bitfield-Mask: 0x01)                          */
#define TRNG_CTRL_KEYWIPE_SHIFT             (15UL)                    /*!< KEYWIPE (Bit 15)                                      */
#define TRNG_CTRL_KEYWIPE_MASK              (0x8000UL)                /*!< KEYWIPE (Bitfield-Mask: 0x01)                         */
/* ========================================================  STATUS  ========================================================= */
#define TRNG_STATUS_RDY_SHIFT               (0UL)                     /*!< RDY (Bit 0)                                           */
#define TRNG_STATUS_RDY_MASK                (0x1UL)                   /*!< RDY (Bitfield-Mask: 0x01)                             */
/* =========================================================  DATA  ========================================================== */
#define TRNG_DATA_DATA_SHIFT                (0UL)                     /*!< DATA (Bit 0)                                          */
#define TRNG_DATA_DATA_MASK                 (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define UART_CTRL_RX_THD_VAL_SHIFT          (0UL)                     /*!< RX_THD_VAL (Bit 0)                                    */
#define UART_CTRL_RX_THD_VAL_MASK           (0xfUL)                   /*!< RX_THD_VAL (Bitfield-Mask: 0x0f)                      */
#define UART_CTRL_PAR_EN_SHIFT              (4UL)                     /*!< PAR_EN (Bit 4)                                        */
#define UART_CTRL_PAR_EN_MASK               (0x10UL)                  /*!< PAR_EN (Bitfield-Mask: 0x01)                          */
#define UART_CTRL_PAR_EO_SHIFT              (5UL)                     /*!< PAR_EO (Bit 5)                                        */
#define UART_CTRL_PAR_EO_MASK               (0x20UL)                  /*!< PAR_EO (Bitfield-Mask: 0x01)                          */
#define UART_CTRL_PAR_MD_SHIFT              (6UL)                     /*!< PAR_MD (Bit 6)                                        */
#define UART_CTRL_PAR_MD_MASK               (0x40UL)                  /*!< PAR_MD (Bitfield-Mask: 0x01)                          */
#define UART_CTRL_CTS_DIS_SHIFT             (7UL)                     /*!< CTS_DIS (Bit 7)                                       */
#define UART_CTRL_CTS_DIS_MASK              (0x80UL)                  /*!< CTS_DIS (Bitfield-Mask: 0x01)                         */
#define UART_CTRL_TX_FLUSH_SHIFT            (8UL)                     /*!< TX_FLUSH (Bit 8)                                      */
#define UART_CTRL_TX_FLUSH_MASK             (0x100UL)                 /*!< TX_FLUSH (Bitfield-Mask: 0x01)                        */
#define UART_CTRL_RX_FLUSH_SHIFT            (9UL)                     /*!< RX_FLUSH (Bit 9)                                      */
#define UART_CTRL_RX_FLUSH_MASK             (0x200UL)                 /*!< RX_FLUSH (Bitfield-Mask: 0x01)                        */
#define UART_CTRL_CHAR_SIZE_SHIFT           (10UL)                    /*!< CHAR_SIZE (Bit 10)                                    */
#define UART_CTRL_CHAR_SIZE_MASK            (0xc00UL)                 /*!< CHAR_SIZE (Bitfield-Mask: 0x03)                       */
#define UART_CTRL_STOPBITS_SHIFT            (12UL)                    /*!< STOPBITS (Bit 12)                                     */
#define UART_CTRL_STOPBITS_MASK             (0x1000UL)                /*!< STOPBITS (Bitfield-Mask: 0x01)                        */
#define UART_CTRL_HFC_EN_SHIFT              (13UL)                    /*!< HFC_EN (Bit 13)                                       */
#define UART_CTRL_HFC_EN_MASK               (0x2000UL)                /*!< HFC_EN (Bitfield-Mask: 0x01)                          */
#define UART_CTRL_RTSDC_SHIFT               (14UL)                    /*!< RTSDC (Bit 14)                                        */
#define UART_CTRL_RTSDC_MASK                (0x4000UL)                /*!< RTSDC (Bitfield-Mask: 0x01)                           */
#define UART_CTRL_BCLKEN_SHIFT              (15UL)                    /*!< BCLKEN (Bit 15)                                       */
#define UART_CTRL_BCLKEN_MASK               (0x8000UL)                /*!< BCLKEN (Bitfield-Mask: 0x01)                          */
#define UART_CTRL_BCLKSRC_SHIFT             (16UL)                    /*!< BCLKSRC (Bit 16)                                      */
#define UART_CTRL_BCLKSRC_MASK              (0x30000UL)               /*!< BCLKSRC (Bitfield-Mask: 0x03)                         */
#define UART_CTRL_DPFE_EN_SHIFT             (18UL)                    /*!< DPFE_EN (Bit 18)                                      */
#define UART_CTRL_DPFE_EN_MASK              (0x40000UL)               /*!< DPFE_EN (Bitfield-Mask: 0x01)                         */
#define UART_CTRL_BCLKRDY_SHIFT             (19UL)                    /*!< BCLKRDY (Bit 19)                                      */
#define UART_CTRL_BCLKRDY_MASK              (0x80000UL)               /*!< BCLKRDY (Bitfield-Mask: 0x01)                         */
#define UART_CTRL_UCAGM_SHIFT               (20UL)                    /*!< UCAGM (Bit 20)                                        */
#define UART_CTRL_UCAGM_MASK                (0x100000UL)              /*!< UCAGM (Bitfield-Mask: 0x01)                           */
#define UART_CTRL_FDM_SHIFT                 (21UL)                    /*!< FDM (Bit 21)                                          */
#define UART_CTRL_FDM_MASK                  (0x200000UL)              /*!< FDM (Bitfield-Mask: 0x01)                             */
#define UART_CTRL_DESM_SHIFT                (22UL)                    /*!< DESM (Bit 22)                                         */
#define UART_CTRL_DESM_MASK                 (0x400000UL)              /*!< DESM (Bitfield-Mask: 0x01)                            */
/* ========================================================  STATUS  ========================================================= */
#define UART_STATUS_TX_BUSY_SHIFT           (0UL)                     /*!< TX_BUSY (Bit 0)                                       */
#define UART_STATUS_TX_BUSY_MASK            (0x1UL)                   /*!< TX_BUSY (Bitfield-Mask: 0x01)                         */
#define UART_STATUS_RX_BUSY_SHIFT           (1UL)                     /*!< RX_BUSY (Bit 1)                                       */
#define UART_STATUS_RX_BUSY_MASK            (0x2UL)                   /*!< RX_BUSY (Bitfield-Mask: 0x01)                         */
#define UART_STATUS_RX_EM_SHIFT             (4UL)                     /*!< RX_EM (Bit 4)                                         */
#define UART_STATUS_RX_EM_MASK              (0x10UL)                  /*!< RX_EM (Bitfield-Mask: 0x01)                           */
#define UART_STATUS_RX_FULL_SHIFT           (5UL)                     /*!< RX_FULL (Bit 5)                                       */
#define UART_STATUS_RX_FULL_MASK            (0x20UL)                  /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define UART_STATUS_TX_EM_SHIFT             (6UL)                     /*!< TX_EM (Bit 6)                                         */
#define UART_STATUS_TX_EM_MASK              (0x40UL)                  /*!< TX_EM (Bitfield-Mask: 0x01)                           */
#define UART_STATUS_TX_FULL_SHIFT           (7UL)                     /*!< TX_FULL (Bit 7)                                       */
#define UART_STATUS_TX_FULL_MASK            (0x80UL)                  /*!< TX_FULL (Bitfield-Mask: 0x01)                         */
#define UART_STATUS_RX_LVL_SHIFT            (8UL)                     /*!< RX_LVL (Bit 8)                                        */
#define UART_STATUS_RX_LVL_MASK             (0xf00UL)                 /*!< RX_LVL (Bitfield-Mask: 0x0f)                          */
#define UART_STATUS_TX_LVL_SHIFT            (12UL)                    /*!< TX_LVL (Bit 12)                                       */
#define UART_STATUS_TX_LVL_MASK             (0xf000UL)                /*!< TX_LVL (Bitfield-Mask: 0x0f)                          */
/* ========================================================  INT_EN  ========================================================= */
#define UART_INT_EN_RX_FERR_SHIFT           (0UL)                     /*!< RX_FERR (Bit 0)                                       */
#define UART_INT_EN_RX_FERR_MASK            (0x1UL)                   /*!< RX_FERR (Bitfield-Mask: 0x01)                         */
#define UART_INT_EN_RX_PAR_SHIFT            (1UL)                     /*!< RX_PAR (Bit 1)                                        */
#define UART_INT_EN_RX_PAR_MASK             (0x2UL)                   /*!< RX_PAR (Bitfield-Mask: 0x01)                          */
#define UART_INT_EN_CTS_EV_SHIFT            (2UL)                     /*!< CTS_EV (Bit 2)                                        */
#define UART_INT_EN_CTS_EV_MASK             (0x4UL)                   /*!< CTS_EV (Bitfield-Mask: 0x01)                          */
#define UART_INT_EN_RX_OV_SHIFT             (3UL)                     /*!< RX_OV (Bit 3)                                         */
#define UART_INT_EN_RX_OV_MASK              (0x8UL)                   /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define UART_INT_EN_RX_THD_SHIFT            (4UL)                     /*!< RX_THD (Bit 4)                                        */
#define UART_INT_EN_RX_THD_MASK             (0x10UL)                  /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define UART_INT_EN_TX_HE_SHIFT             (6UL)                     /*!< TX_HE (Bit 6)                                         */
#define UART_INT_EN_TX_HE_MASK              (0x40UL)                  /*!< TX_HE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INT_FL  ========================================================= */
#define UART_INT_FL_RX_FERR_SHIFT           (0UL)                     /*!< RX_FERR (Bit 0)                                       */
#define UART_INT_FL_RX_FERR_MASK            (0x1UL)                   /*!< RX_FERR (Bitfield-Mask: 0x01)                         */
#define UART_INT_FL_RX_PAR_SHIFT            (1UL)                     /*!< RX_PAR (Bit 1)                                        */
#define UART_INT_FL_RX_PAR_MASK             (0x2UL)                   /*!< RX_PAR (Bitfield-Mask: 0x01)                          */
#define UART_INT_FL_CTS_EV_SHIFT            (2UL)                     /*!< CTS_EV (Bit 2)                                        */
#define UART_INT_FL_CTS_EV_MASK             (0x4UL)                   /*!< CTS_EV (Bitfield-Mask: 0x01)                          */
#define UART_INT_FL_RX_OV_SHIFT             (3UL)                     /*!< RX_OV (Bit 3)                                         */
#define UART_INT_FL_RX_OV_MASK              (0x8UL)                   /*!< RX_OV (Bitfield-Mask: 0x01)                           */
#define UART_INT_FL_RX_THD_SHIFT            (4UL)                     /*!< RX_THD (Bit 4)                                        */
#define UART_INT_FL_RX_THD_MASK             (0x10UL)                  /*!< RX_THD (Bitfield-Mask: 0x01)                          */
#define UART_INT_FL_TX_HE_SHIFT             (6UL)                     /*!< TX_HE (Bit 6)                                         */
#define UART_INT_FL_TX_HE_MASK              (0x40UL)                  /*!< TX_HE (Bitfield-Mask: 0x01)                           */
/* ========================================================  CLKDIV  ========================================================= */
#define UART_CLKDIV_CLKDIV_SHIFT            (0UL)                     /*!< CLKDIV (Bit 0)                                        */
#define UART_CLKDIV_CLKDIV_MASK             (0xfffffUL)               /*!< CLKDIV (Bitfield-Mask: 0xfffff)                       */
/* ==========================================================  OSR  ========================================================== */
#define UART_OSR_OSR_SHIFT                  (0UL)                     /*!< OSR (Bit 0)                                           */
#define UART_OSR_OSR_MASK                   (0x7UL)                   /*!< OSR (Bitfield-Mask: 0x07)                             */
/* ========================================================  TXPEEK  ========================================================= */
#define UART_TXPEEK_DATA_SHIFT              (0UL)                     /*!< DATA (Bit 0)                                          */
#define UART_TXPEEK_DATA_MASK               (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* ==========================================================  PNR  ========================================================== */
#define UART_PNR_CTS_SHIFT                  (0UL)                     /*!< CTS (Bit 0)                                           */
#define UART_PNR_CTS_MASK                   (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UART_PNR_RTS_SHIFT                  (1UL)                     /*!< RTS (Bit 1)                                           */
#define UART_PNR_RTS_MASK                   (0x2UL)                   /*!< RTS (Bitfield-Mask: 0x01)                             */
/* =========================================================  FIFO  ========================================================== */
#define UART_FIFO_DATA_SHIFT                (0UL)                     /*!< DATA (Bit 0)                                          */
#define UART_FIFO_DATA_MASK                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
#define UART_FIFO_RX_PAR_SHIFT              (8UL)                     /*!< RX_PAR (Bit 8)                                        */
#define UART_FIFO_RX_PAR_MASK               (0x100UL)                 /*!< RX_PAR (Bitfield-Mask: 0x01)                          */
/* ==========================================================  DMA  ========================================================== */
#define UART_DMA_TX_THD_VAL_SHIFT           (0UL)                     /*!< TX_THD_VAL (Bit 0)                                    */
#define UART_DMA_TX_THD_VAL_MASK            (0xfUL)                   /*!< TX_THD_VAL (Bitfield-Mask: 0x0f)                      */
#define UART_DMA_TX_EN_SHIFT                (4UL)                     /*!< TX_EN (Bit 4)                                         */
#define UART_DMA_TX_EN_MASK                 (0x10UL)                  /*!< TX_EN (Bitfield-Mask: 0x01)                           */
#define UART_DMA_RX_THD_VAL_SHIFT           (5UL)                     /*!< RX_THD_VAL (Bit 5)                                    */
#define UART_DMA_RX_THD_VAL_MASK            (0x1e0UL)                 /*!< RX_THD_VAL (Bitfield-Mask: 0x0f)                      */
#define UART_DMA_RX_EN_SHIFT                (9UL)                     /*!< RX_EN (Bit 9)                                         */
#define UART_DMA_RX_EN_MASK                 (0x200UL)                 /*!< RX_EN (Bitfield-Mask: 0x01)                           */
/* =========================================================  WKEN  ========================================================== */
#define UART_WKEN_RX_NE_SHIFT               (0UL)                     /*!< RX_NE (Bit 0)                                         */
#define UART_WKEN_RX_NE_MASK                (0x1UL)                   /*!< RX_NE (Bitfield-Mask: 0x01)                           */
#define UART_WKEN_RX_FULL_SHIFT             (1UL)                     /*!< RX_FULL (Bit 1)                                       */
#define UART_WKEN_RX_FULL_MASK              (0x2UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define UART_WKEN_RX_THD_SHIFT              (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define UART_WKEN_RX_THD_MASK               (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */
/* =========================================================  WKFL  ========================================================== */
#define UART_WKFL_RX_NE_SHIFT               (0UL)                     /*!< RX_NE (Bit 0)                                         */
#define UART_WKFL_RX_NE_MASK                (0x1UL)                   /*!< RX_NE (Bitfield-Mask: 0x01)                           */
#define UART_WKFL_RX_FULL_SHIFT             (1UL)                     /*!< RX_FULL (Bit 1)                                       */
#define UART_WKFL_RX_FULL_MASK              (0x2UL)                   /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
#define UART_WKFL_RX_THD_SHIFT              (2UL)                     /*!< RX_THD (Bit 2)                                        */
#define UART_WKFL_RX_THD_MASK               (0x4UL)                   /*!< RX_THD (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define WDT_CTRL_INT_LATE_VAL_SHIFT         (0UL)                     /*!< INT_LATE_VAL (Bit 0)                                  */
#define WDT_CTRL_INT_LATE_VAL_MASK          (0xfUL)                   /*!< INT_LATE_VAL (Bitfield-Mask: 0x0f)                    */
#define WDT_CTRL_RST_LATE_VAL_SHIFT         (4UL)                     /*!< RST_LATE_VAL (Bit 4)                                  */
#define WDT_CTRL_RST_LATE_VAL_MASK          (0xf0UL)                  /*!< RST_LATE_VAL (Bitfield-Mask: 0x0f)                    */
#define WDT_CTRL_EN_SHIFT                   (8UL)                     /*!< EN (Bit 8)                                            */
#define WDT_CTRL_EN_MASK                    (0x100UL)                 /*!< EN (Bitfield-Mask: 0x01)                              */
#define WDT_CTRL_INT_LATE_SHIFT             (9UL)                     /*!< INT_LATE (Bit 9)                                      */
#define WDT_CTRL_INT_LATE_MASK              (0x200UL)                 /*!< INT_LATE (Bitfield-Mask: 0x01)                        */
#define WDT_CTRL_WDT_INT_EN_SHIFT           (10UL)                    /*!< WDT_INT_EN (Bit 10)                                   */
#define WDT_CTRL_WDT_INT_EN_MASK            (0x400UL)                 /*!< WDT_INT_EN (Bitfield-Mask: 0x01)                      */
#define WDT_CTRL_WDT_RST_EN_SHIFT           (11UL)                    /*!< WDT_RST_EN (Bit 11)                                   */
#define WDT_CTRL_WDT_RST_EN_MASK            (0x800UL)                 /*!< WDT_RST_EN (Bitfield-Mask: 0x01)                      */
#define WDT_CTRL_INT_EARLY_SHIFT            (12UL)                    /*!< INT_EARLY (Bit 12)                                    */
#define WDT_CTRL_INT_EARLY_MASK             (0x1000UL)                /*!< INT_EARLY (Bitfield-Mask: 0x01)                       */
#define WDT_CTRL_INT_EARLY_VAL_SHIFT        (16UL)                    /*!< INT_EARLY_VAL (Bit 16)                                */
#define WDT_CTRL_INT_EARLY_VAL_MASK         (0xf0000UL)               /*!< INT_EARLY_VAL (Bitfield-Mask: 0x0f)                   */
#define WDT_CTRL_RST_EARLY_VAL_SHIFT        (20UL)                    /*!< RST_EARLY_VAL (Bit 20)                                */
#define WDT_CTRL_RST_EARLY_VAL_MASK         (0xf00000UL)              /*!< RST_EARLY_VAL (Bitfield-Mask: 0x0f)                   */
#define WDT_CTRL_CLKRDY_IE_SHIFT            (27UL)                    /*!< CLKRDY_IE (Bit 27)                                    */
#define WDT_CTRL_CLKRDY_IE_MASK             (0x8000000UL)             /*!< CLKRDY_IE (Bitfield-Mask: 0x01)                       */
#define WDT_CTRL_CLKRDY_SHIFT               (28UL)                    /*!< CLKRDY (Bit 28)                                       */
#define WDT_CTRL_CLKRDY_MASK                (0x10000000UL)            /*!< CLKRDY (Bitfield-Mask: 0x01)                          */
#define WDT_CTRL_WIN_EN_SHIFT               (29UL)                    /*!< WIN_EN (Bit 29)                                       */
#define WDT_CTRL_WIN_EN_MASK                (0x20000000UL)            /*!< WIN_EN (Bitfield-Mask: 0x01)                          */
#define WDT_CTRL_RST_EARLY_SHIFT            (30UL)                    /*!< RST_EARLY (Bit 30)                                    */
#define WDT_CTRL_RST_EARLY_MASK             (0x40000000UL)            /*!< RST_EARLY (Bitfield-Mask: 0x01)                       */
#define WDT_CTRL_RST_LATE_SHIFT             (31UL)                    /*!< RST_LATE (Bit 31)                                     */
#define WDT_CTRL_RST_LATE_MASK              (0x80000000UL)            /*!< RST_LATE (Bitfield-Mask: 0x01)                        */
/* ==========================================================  RST  ========================================================== */
#define WDT_RST_RESET_SHIFT                 (0UL)                     /*!< RESET (Bit 0)                                         */
#define WDT_RST_RESET_MASK                  (0xffUL)                  /*!< RESET (Bitfield-Mask: 0xff)                           */
/* ========================================================  CLKSEL  ========================================================= */
#define WDT_CLKSEL_SOURCE_SHIFT             (0UL)                     /*!< SOURCE (Bit 0)                                        */
#define WDT_CLKSEL_SOURCE_MASK              (0x7UL)                   /*!< SOURCE (Bitfield-Mask: 0x07)                          */
/* ==========================================================  CNT  ========================================================== */
#define WDT_CNT_COUNT_SHIFT                 (0UL)                     /*!< COUNT (Bit 0)                                         */
#define WDT_CNT_COUNT_MASK                  (0xffffffffUL)            /*!< COUNT (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                           SIMO                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  VREGO_A  ======================================================== */
#define SIMO_VREGO_A_VSETA_SHIFT            (0UL)                     /*!< VSETA (Bit 0)                                         */
#define SIMO_VREGO_A_VSETA_MASK             (0x7fUL)                  /*!< VSETA (Bitfield-Mask: 0x7f)                           */
#define SIMO_VREGO_A_RANGEA_SHIFT           (7UL)                     /*!< RANGEA (Bit 7)                                        */
#define SIMO_VREGO_A_RANGEA_MASK            (0x80UL)                  /*!< RANGEA (Bitfield-Mask: 0x01)                          */
/* ========================================================  VREGO_B  ======================================================== */
#define SIMO_VREGO_B_VSETB_SHIFT            (0UL)                     /*!< VSETB (Bit 0)                                         */
#define SIMO_VREGO_B_VSETB_MASK             (0x7fUL)                  /*!< VSETB (Bitfield-Mask: 0x7f)                           */
#define SIMO_VREGO_B_RANGEB_SHIFT           (7UL)                     /*!< RANGEB (Bit 7)                                        */
#define SIMO_VREGO_B_RANGEB_MASK            (0x80UL)                  /*!< RANGEB (Bitfield-Mask: 0x01)                          */
/* ========================================================  VREGO_C  ======================================================== */
#define SIMO_VREGO_C_VSETC_SHIFT            (0UL)                     /*!< VSETC (Bit 0)                                         */
#define SIMO_VREGO_C_VSETC_MASK             (0x7fUL)                  /*!< VSETC (Bitfield-Mask: 0x7f)                           */
#define SIMO_VREGO_C_RANGEC_SHIFT           (7UL)                     /*!< RANGEC (Bit 7)                                        */
#define SIMO_VREGO_C_RANGEC_MASK            (0x80UL)                  /*!< RANGEC (Bitfield-Mask: 0x01)                          */
/* ========================================================  VREGO_D  ======================================================== */
#define SIMO_VREGO_D_VSETD_SHIFT            (0UL)                     /*!< VSETD (Bit 0)                                         */
#define SIMO_VREGO_D_VSETD_MASK             (0x7fUL)                  /*!< VSETD (Bitfield-Mask: 0x7f)                           */
#define SIMO_VREGO_D_RANGED_SHIFT           (7UL)                     /*!< RANGED (Bit 7)                                        */
#define SIMO_VREGO_D_RANGED_MASK            (0x80UL)                  /*!< RANGED (Bitfield-Mask: 0x01)                          */
/* =========================================================  IPKA  ========================================================== */
#define SIMO_IPKA_IPKSETA_SHIFT             (0UL)                     /*!< IPKSETA (Bit 0)                                       */
#define SIMO_IPKA_IPKSETA_MASK              (0xfUL)                   /*!< IPKSETA (Bitfield-Mask: 0x0f)                         */
#define SIMO_IPKA_IPKSETB_SHIFT             (4UL)                     /*!< IPKSETB (Bit 4)                                       */
#define SIMO_IPKA_IPKSETB_MASK              (0xf0UL)                  /*!< IPKSETB (Bitfield-Mask: 0x0f)                         */
/* =========================================================  IPKB  ========================================================== */
#define SIMO_IPKB_IPKSETC_SHIFT             (0UL)                     /*!< IPKSETC (Bit 0)                                       */
#define SIMO_IPKB_IPKSETC_MASK              (0xfUL)                   /*!< IPKSETC (Bitfield-Mask: 0x0f)                         */
#define SIMO_IPKB_IPKSETD_SHIFT             (4UL)                     /*!< IPKSETD (Bit 4)                                       */
#define SIMO_IPKB_IPKSETD_MASK              (0xf0UL)                  /*!< IPKSETD (Bitfield-Mask: 0x0f)                         */
/* ========================================================  MAXTON  ========================================================= */
#define SIMO_MAXTON_TONSET_SHIFT            (0UL)                     /*!< TONSET (Bit 0)                                        */
#define SIMO_MAXTON_TONSET_MASK             (0xfUL)                   /*!< TONSET (Bitfield-Mask: 0x0f)                          */
/* ========================================================  ILOAD_A  ======================================================== */
#define SIMO_ILOAD_A_ILOADA_SHIFT           (0UL)                     /*!< ILOADA (Bit 0)                                        */
#define SIMO_ILOAD_A_ILOADA_MASK            (0xffUL)                  /*!< ILOADA (Bitfield-Mask: 0xff)                          */
/* ========================================================  ILOAD_B  ======================================================== */
#define SIMO_ILOAD_B_ILOADB_SHIFT           (0UL)                     /*!< ILOADB (Bit 0)                                        */
#define SIMO_ILOAD_B_ILOADB_MASK            (0xffUL)                  /*!< ILOADB (Bitfield-Mask: 0xff)                          */
/* ========================================================  ILOAD_C  ======================================================== */
#define SIMO_ILOAD_C_ILOADC_SHIFT           (0UL)                     /*!< ILOADC (Bit 0)                                        */
#define SIMO_ILOAD_C_ILOADC_MASK            (0xffUL)                  /*!< ILOADC (Bitfield-Mask: 0xff)                          */
/* ========================================================  ILOAD_D  ======================================================== */
#define SIMO_ILOAD_D_ILOADD_SHIFT           (0UL)                     /*!< ILOADD (Bit 0)                                        */
#define SIMO_ILOAD_D_ILOADD_MASK            (0xffUL)                  /*!< ILOADD (Bitfield-Mask: 0xff)                          */
/* ===================================================  BUCK_ALERT_THR_A  ==================================================== */
#define SIMO_BUCK_ALERT_THR_A_BUCKTHRA_SHIFT (0UL)                    /*!< BUCKTHRA (Bit 0)                                      */
#define SIMO_BUCK_ALERT_THR_A_BUCKTHRA_MASK  (0xffUL)                 /*!< BUCKTHRA (Bitfield-Mask: 0xff)                        */
/* ===================================================  BUCK_ALERT_THR_B  ==================================================== */
#define SIMO_BUCK_ALERT_THR_B_BUCKTHRB_SHIFT (0UL)                    /*!< BUCKTHRB (Bit 0)                                      */
#define SIMO_BUCK_ALERT_THR_B_BUCKTHRB_MASK  (0xffUL)                 /*!< BUCKTHRB (Bitfield-Mask: 0xff)                        */
/* ===================================================  BUCK_ALERT_THR_C  ==================================================== */
#define SIMO_BUCK_ALERT_THR_C_BUCKTHRC_SHIFT (0UL)                    /*!< BUCKTHRC (Bit 0)                                      */
#define SIMO_BUCK_ALERT_THR_C_BUCKTHRC_MASK  (0xffUL)                 /*!< BUCKTHRC (Bitfield-Mask: 0xff)                        */
/* ===================================================  BUCK_ALERT_THR_D  ==================================================== */
#define SIMO_BUCK_ALERT_THR_D_BUCKTHRD_SHIFT (0UL)                    /*!< BUCKTHRD (Bit 0)                                      */
#define SIMO_BUCK_ALERT_THR_D_BUCKTHRD_MASK  (0xffUL)                 /*!< BUCKTHRD (Bitfield-Mask: 0xff)                        */
/* ====================================================  BUCK_OUT_READY  ===================================================== */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYA_SHIFT (0UL)                   /*!< BUCKOUTRDYA (Bit 0)                                   */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYA_MASK  (0x1UL)                 /*!< BUCKOUTRDYA (Bitfield-Mask: 0x01)                     */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYB_SHIFT (1UL)                   /*!< BUCKOUTRDYB (Bit 1)                                   */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYB_MASK  (0x2UL)                 /*!< BUCKOUTRDYB (Bitfield-Mask: 0x01)                     */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYC_SHIFT (2UL)                   /*!< BUCKOUTRDYC (Bit 2)                                   */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYC_MASK  (0x4UL)                 /*!< BUCKOUTRDYC (Bitfield-Mask: 0x01)                     */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYD_SHIFT (3UL)                   /*!< BUCKOUTRDYD (Bit 3)                                   */
#define SIMO_BUCK_OUT_READY_BUCKOUTRDYD_MASK  (0x8UL)                 /*!< BUCKOUTRDYD (Bitfield-Mask: 0x01)                     */
/* ===================================================  ZERO_CROSS_CAL_A  ==================================================== */
#define SIMO_ZERO_CROSS_CAL_A_ZXCALA_SHIFT  (0UL)                     /*!< ZXCALA (Bit 0)                                        */
#define SIMO_ZERO_CROSS_CAL_A_ZXCALA_MASK   (0xfUL)                   /*!< ZXCALA (Bitfield-Mask: 0x0f)                          */
/* ===================================================  ZERO_CROSS_CAL_B  ==================================================== */
#define SIMO_ZERO_CROSS_CAL_B_ZXCALB_SHIFT  (0UL)                     /*!< ZXCALB (Bit 0)                                        */
#define SIMO_ZERO_CROSS_CAL_B_ZXCALB_MASK   (0xfUL)                   /*!< ZXCALB (Bitfield-Mask: 0x0f)                          */
/* ===================================================  ZERO_CROSS_CAL_C  ==================================================== */
#define SIMO_ZERO_CROSS_CAL_C_ZXCALC_SHIFT  (0UL)                     /*!< ZXCALC (Bit 0)                                        */
#define SIMO_ZERO_CROSS_CAL_C_ZXCALC_MASK   (0xfUL)                   /*!< ZXCALC (Bitfield-Mask: 0x0f)                          */
/* ===================================================  ZERO_CROSS_CAL_D  ==================================================== */
#define SIMO_ZERO_CROSS_CAL_D_ZXCALD_SHIFT  (0UL)                     /*!< ZXCALD (Bit 0)                                        */
#define SIMO_ZERO_CROSS_CAL_D_ZXCALD_MASK   (0xfUL)                   /*!< ZXCALD (Bitfield-Mask: 0x0f)                          */


/* =========================================================================================================================== */
/* ================                                           SEMA                                            ================ */
/* =========================================================================================================================== */

/* ======================================================  SEMAPHORES  ======================================================= */
#define SEMA_SEMAPHORES_SEMA_SHIFT          (0UL)                     /*!< sema (Bit 0)                                          */
#define SEMA_SEMAPHORES_SEMA_MASK           (0x1UL)                   /*!< sema (Bitfield-Mask: 0x01)                            */
/* =========================================================  irq0  ========================================================== */
#define SEMA_IRQ0_EN_SHIFT                  (0UL)                     /*!< en (Bit 0)                                            */
#define SEMA_IRQ0_EN_MASK                   (0x1UL)                   /*!< en (Bitfield-Mask: 0x01)                              */
#define SEMA_IRQ0_CM4_IRQ_SHIFT             (16UL)                    /*!< cm4_irq (Bit 16)                                      */
#define SEMA_IRQ0_CM4_IRQ_MASK              (0x10000UL)               /*!< cm4_irq (Bitfield-Mask: 0x01)                         */
/* =========================================================  mail0  ========================================================= */
#define SEMA_MAIL0_DATA_SHIFT               (0UL)                     /*!< data (Bit 0)                                          */
#define SEMA_MAIL0_DATA_MASK                (0xffffffffUL)            /*!< data (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  irq1  ========================================================== */
#define SEMA_IRQ1_EN_SHIFT                  (0UL)                     /*!< en (Bit 0)                                            */
#define SEMA_IRQ1_EN_MASK                   (0x1UL)                   /*!< en (Bitfield-Mask: 0x01)                              */
#define SEMA_IRQ1_RV32_IRQ_SHIFT            (16UL)                    /*!< rv32_irq (Bit 16)                                     */
#define SEMA_IRQ1_RV32_IRQ_MASK             (0x10000UL)               /*!< rv32_irq (Bitfield-Mask: 0x01)                        */
/* =========================================================  mail1  ========================================================= */
#define SEMA_MAIL1_DATA_SHIFT               (0UL)                     /*!< data (Bit 0)                                          */
#define SEMA_MAIL1_DATA_MASK                (0xffffffffUL)            /*!< data (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  status  ========================================================= */
#define SEMA_STATUS_STATUS0_SHIFT           (0UL)                     /*!< status0 (Bit 0)                                       */
#define SEMA_STATUS_STATUS0_MASK            (0x1UL)                   /*!< status0 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS1_SHIFT           (1UL)                     /*!< status1 (Bit 1)                                       */
#define SEMA_STATUS_STATUS1_MASK            (0x2UL)                   /*!< status1 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS2_SHIFT           (2UL)                     /*!< status2 (Bit 2)                                       */
#define SEMA_STATUS_STATUS2_MASK            (0x4UL)                   /*!< status2 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS3_SHIFT           (3UL)                     /*!< status3 (Bit 3)                                       */
#define SEMA_STATUS_STATUS3_MASK            (0x8UL)                   /*!< status3 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS4_SHIFT           (4UL)                     /*!< status4 (Bit 4)                                       */
#define SEMA_STATUS_STATUS4_MASK            (0x10UL)                  /*!< status4 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS5_SHIFT           (5UL)                     /*!< status5 (Bit 5)                                       */
#define SEMA_STATUS_STATUS5_MASK            (0x20UL)                  /*!< status5 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS6_SHIFT           (6UL)                     /*!< status6 (Bit 6)                                       */
#define SEMA_STATUS_STATUS6_MASK            (0x40UL)                  /*!< status6 (Bitfield-Mask: 0x01)                         */
#define SEMA_STATUS_STATUS7_SHIFT           (7UL)                     /*!< status7 (Bit 7)                                       */
#define SEMA_STATUS_STATUS7_MASK            (0x80UL)                  /*!< status7 (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                            FCR                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  FCTRL0  ========================================================= */
#define FCR_FCTRL0_I2C0DGEN0_SHIFT          (20UL)                    /*!< I2C0DGEN0 (Bit 20)                                    */
#define FCR_FCTRL0_I2C0DGEN0_MASK           (0x100000UL)              /*!< I2C0DGEN0 (Bitfield-Mask: 0x01)                       */
#define FCR_FCTRL0_I2C0DGEN1_SHIFT          (21UL)                    /*!< I2C0DGEN1 (Bit 21)                                    */
#define FCR_FCTRL0_I2C0DGEN1_MASK           (0x200000UL)              /*!< I2C0DGEN1 (Bitfield-Mask: 0x01)                       */
#define FCR_FCTRL0_I2C1DGEN0_SHIFT          (22UL)                    /*!< I2C1DGEN0 (Bit 22)                                    */
#define FCR_FCTRL0_I2C1DGEN0_MASK           (0x400000UL)              /*!< I2C1DGEN0 (Bitfield-Mask: 0x01)                       */
#define FCR_FCTRL0_I2C1DGEN1_SHIFT          (23UL)                    /*!< I2C1DGEN1 (Bit 23)                                    */
#define FCR_FCTRL0_I2C1DGEN1_MASK           (0x800000UL)              /*!< I2C1DGEN1 (Bitfield-Mask: 0x01)                       */
#define FCR_FCTRL0_I2C2DGEN0_SHIFT          (24UL)                    /*!< I2C2DGEN0 (Bit 24)                                    */
#define FCR_FCTRL0_I2C2DGEN0_MASK           (0x1000000UL)             /*!< I2C2DGEN0 (Bitfield-Mask: 0x01)                       */
#define FCR_FCTRL0_I2C2DGEN1_SHIFT          (25UL)                    /*!< I2C2DGEN1 (Bit 25)                                    */
#define FCR_FCTRL0_I2C2DGEN1_MASK           (0x2000000UL)             /*!< I2C2DGEN1 (Bitfield-Mask: 0x01)                       */
/* =======================================================  AUTOCAL0  ======================================================== */
#define FCR_AUTOCAL0_ACEN_SHIFT             (0UL)                     /*!< ACEN (Bit 0)                                          */
#define FCR_AUTOCAL0_ACEN_MASK              (0x1UL)                   /*!< ACEN (Bitfield-Mask: 0x01)                            */
#define FCR_AUTOCAL0_ACRUN_SHIFT            (1UL)                     /*!< ACRUN (Bit 1)                                         */
#define FCR_AUTOCAL0_ACRUN_MASK             (0x2UL)                   /*!< ACRUN (Bitfield-Mask: 0x01)                           */
#define FCR_AUTOCAL0_LDTRM_SHIFT            (2UL)                     /*!< LDTRM (Bit 2)                                         */
#define FCR_AUTOCAL0_LDTRM_MASK             (0x4UL)                   /*!< LDTRM (Bitfield-Mask: 0x01)                           */
#define FCR_AUTOCAL0_GAININV_SHIFT          (3UL)                     /*!< GAININV (Bit 3)                                       */
#define FCR_AUTOCAL0_GAININV_MASK           (0x8UL)                   /*!< GAININV (Bitfield-Mask: 0x01)                         */
#define FCR_AUTOCAL0_ATOMIC_SHIFT           (4UL)                     /*!< ATOMIC (Bit 4)                                        */
#define FCR_AUTOCAL0_ATOMIC_MASK            (0x10UL)                  /*!< ATOMIC (Bitfield-Mask: 0x01)                          */
#define FCR_AUTOCAL0_MU_SHIFT               (8UL)                     /*!< MU (Bit 8)                                            */
#define FCR_AUTOCAL0_MU_MASK                (0xfff00UL)               /*!< MU (Bitfield-Mask: 0xfff)                             */
#define FCR_AUTOCAL0_HIRC96MACTMROUT_SHIFT  (23UL)                    /*!< HIRC96MACTMROUT (Bit 23)                              */
#define FCR_AUTOCAL0_HIRC96MACTMROUT_MASK   (0xff800000UL)            /*!< HIRC96MACTMROUT (Bitfield-Mask: 0x1ff)                */
/* =======================================================  AUTOCAL1  ======================================================== */
#define FCR_AUTOCAL1_INITTRM_SHIFT          (0UL)                     /*!< INITTRM (Bit 0)                                       */
#define FCR_AUTOCAL1_INITTRM_MASK           (0x1ffUL)                 /*!< INITTRM (Bitfield-Mask: 0x1ff)                        */
/* =======================================================  AUTOCAL2  ======================================================== */
#define FCR_AUTOCAL2_DONECNT_SHIFT          (0UL)                     /*!< DONECNT (Bit 0)                                       */
#define FCR_AUTOCAL2_DONECNT_MASK           (0xffUL)                  /*!< DONECNT (Bitfield-Mask: 0xff)                         */
#define FCR_AUTOCAL2_ACDIV_SHIFT            (8UL)                     /*!< ACDIV (Bit 8)                                         */
#define FCR_AUTOCAL2_ACDIV_MASK             (0x1fff00UL)              /*!< ACDIV (Bitfield-Mask: 0x1fff)                         */
/* ======================================================  URVBOOTADDR  ====================================================== */
/* ========================================================  URVCTRL  ======================================================== */
#define FCR_URVCTRL_MEMSEL_SHIFT            (0UL)                     /*!< MEMSEL (Bit 0)                                        */
#define FCR_URVCTRL_MEMSEL_MASK             (0x1UL)                   /*!< MEMSEL (Bitfield-Mask: 0x01)                          */
#define FCR_URVCTRL_IFLUSHEN_SHIFT          (1UL)                     /*!< IFLUSHEN (Bit 1)                                      */
#define FCR_URVCTRL_IFLUSHEN_MASK           (0x2UL)                   /*!< IFLUSHEN (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                           GCFR                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  REG0  ========================================================== */
#define GCFR_REG0_CNNX16_0_PWR_EN_SHIFT     (0UL)                     /*!< cnnx16_0_pwr_en (Bit 0)                               */
#define GCFR_REG0_CNNX16_0_PWR_EN_MASK      (0x1UL)                   /*!< cnnx16_0_pwr_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG0_CNNX16_1_PWR_EN_SHIFT     (1UL)                     /*!< cnnx16_1_pwr_en (Bit 1)                               */
#define GCFR_REG0_CNNX16_1_PWR_EN_MASK      (0x2UL)                   /*!< cnnx16_1_pwr_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG0_CNNX16_2_PWR_EN_SHIFT     (2UL)                     /*!< cnnx16_2_pwr_en (Bit 2)                               */
#define GCFR_REG0_CNNX16_2_PWR_EN_MASK      (0x4UL)                   /*!< cnnx16_2_pwr_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG0_CNNX16_3_PWR_EN_SHIFT     (3UL)                     /*!< cnnx16_3_pwr_en (Bit 3)                               */
#define GCFR_REG0_CNNX16_3_PWR_EN_MASK      (0x8UL)                   /*!< cnnx16_3_pwr_en (Bitfield-Mask: 0x01)                 */
/* =========================================================  REG1  ========================================================== */
#define GCFR_REG1_CNNX16_0_RAM_EN_SHIFT     (0UL)                     /*!< cnnx16_0_ram_en (Bit 0)                               */
#define GCFR_REG1_CNNX16_0_RAM_EN_MASK      (0x1UL)                   /*!< cnnx16_0_ram_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG1_CNNX16_1_RAM_EN_SHIFT     (1UL)                     /*!< cnnx16_1_ram_en (Bit 1)                               */
#define GCFR_REG1_CNNX16_1_RAM_EN_MASK      (0x2UL)                   /*!< cnnx16_1_ram_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG1_CNNX16_2_RAM_EN_SHIFT     (2UL)                     /*!< cnnx16_2_ram_en (Bit 2)                               */
#define GCFR_REG1_CNNX16_2_RAM_EN_MASK      (0x4UL)                   /*!< cnnx16_2_ram_en (Bitfield-Mask: 0x01)                 */
#define GCFR_REG1_CNNX16_3_RAM_EN_SHIFT     (3UL)                     /*!< cnnx16_3_ram_en (Bit 3)                               */
#define GCFR_REG1_CNNX16_3_RAM_EN_MASK      (0x8UL)                   /*!< cnnx16_3_ram_en (Bitfield-Mask: 0x01)                 */
/* =========================================================  REG2  ========================================================== */
#define GCFR_REG2_CNNX16_0_ISO_SHIFT        (0UL)                     /*!< cnnx16_0_iso (Bit 0)                                  */
#define GCFR_REG2_CNNX16_0_ISO_MASK         (0x1UL)                   /*!< cnnx16_0_iso (Bitfield-Mask: 0x01)                    */
#define GCFR_REG2_CNNX16_1_ISO_SHIFT        (1UL)                     /*!< cnnx16_1_iso (Bit 1)                                  */
#define GCFR_REG2_CNNX16_1_ISO_MASK         (0x2UL)                   /*!< cnnx16_1_iso (Bitfield-Mask: 0x01)                    */
#define GCFR_REG2_CNNX16_2_ISO_SHIFT        (2UL)                     /*!< cnnx16_2_iso (Bit 2)                                  */
#define GCFR_REG2_CNNX16_2_ISO_MASK         (0x4UL)                   /*!< cnnx16_2_iso (Bitfield-Mask: 0x01)                    */
#define GCFR_REG2_CNNX16_3_ISO_SHIFT        (3UL)                     /*!< cnnx16_3_iso (Bit 3)                                  */
#define GCFR_REG2_CNNX16_3_ISO_MASK         (0x8UL)                   /*!< cnnx16_3_iso (Bitfield-Mask: 0x01)                    */
/* =========================================================  REG3  ========================================================== */
#define GCFR_REG3_CNNX16_0_RST_SHIFT        (0UL)                     /*!< cnnx16_0_rst (Bit 0)                                  */
#define GCFR_REG3_CNNX16_0_RST_MASK         (0x1UL)                   /*!< cnnx16_0_rst (Bitfield-Mask: 0x01)                    */
#define GCFR_REG3_CNNX16_1_RST_SHIFT        (1UL)                     /*!< cnnx16_1_rst (Bit 1)                                  */
#define GCFR_REG3_CNNX16_1_RST_MASK         (0x2UL)                   /*!< cnnx16_1_rst (Bitfield-Mask: 0x01)                    */
#define GCFR_REG3_CNNX16_2_RST_SHIFT        (2UL)                     /*!< cnnx16_2_rst (Bit 2)                                  */
#define GCFR_REG3_CNNX16_2_RST_MASK         (0x4UL)                   /*!< cnnx16_2_rst (Bitfield-Mask: 0x01)                    */
#define GCFR_REG3_CNNX16_3_RST_SHIFT        (3UL)                     /*!< cnnx16_3_rst (Bit 3)                                  */
#define GCFR_REG3_CNNX16_3_RST_MASK         (0x8UL)                   /*!< cnnx16_3_rst (Bitfield-Mask: 0x01)                    */


/* =========================================================================================================================== */
/* ================                                            SIR                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  SISTAT  ========================================================= */
#define SIR_SISTAT_MAGIC_SHIFT              (0UL)                     /*!< MAGIC (Bit 0)                                         */
#define SIR_SISTAT_MAGIC_MASK               (0x1UL)                   /*!< MAGIC (Bitfield-Mask: 0x01)                           */
#define SIR_SISTAT_CRCERR_SHIFT             (1UL)                     /*!< CRCERR (Bit 1)                                        */
#define SIR_SISTAT_CRCERR_MASK              (0x2UL)                   /*!< CRCERR (Bitfield-Mask: 0x01)                          */
/* =========================================================  ADDR  ========================================================== */
#define SIR_ADDR_ERRADDR_SHIFT              (0UL)                     /*!< ERRADDR (Bit 0)                                       */
#define SIR_ADDR_ERRADDR_MASK               (0xffffffffUL)            /*!< ERRADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  FSTAT  ========================================================= */
#define SIR_FSTAT_FPU_SHIFT                 (0UL)                     /*!< FPU (Bit 0)                                           */
#define SIR_FSTAT_FPU_MASK                  (0x1UL)                   /*!< FPU (Bitfield-Mask: 0x01)                             */
#define SIR_FSTAT_ADC_SHIFT                 (2UL)                     /*!< ADC (Bit 2)                                           */
#define SIR_FSTAT_ADC_MASK                  (0x4UL)                   /*!< ADC (Bitfield-Mask: 0x01)                             */
#define SIR_FSTAT_SMPHR_SHIFT               (7UL)                     /*!< SMPHR (Bit 7)                                         */
#define SIR_FSTAT_SMPHR_MASK                (0x80UL)                  /*!< SMPHR (Bitfield-Mask: 0x01)                           */
/* ========================================================  SFSTAT  ========================================================= */
#define SIR_SFSTAT_TRNG_SHIFT               (0UL)                     /*!< TRNG (Bit 0)                                          */
#define SIR_SFSTAT_TRNG_MASK                (0x1UL)                   /*!< TRNG (Bitfield-Mask: 0x01)                            */
#define SIR_SFSTAT_AES_SHIFT                (2UL)                     /*!< AES (Bit 2)                                           */
#define SIR_SFSTAT_AES_MASK                 (0x4UL)                   /*!< AES (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                          TRIMSIR                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  RTC  ========================================================== */
#define TRIMSIR_RTC_X1TRIM_SHIFT            (16UL)                    /*!< X1TRIM (Bit 16)                                       */
#define TRIMSIR_RTC_X1TRIM_MASK             (0x1f0000UL)              /*!< X1TRIM (Bitfield-Mask: 0x1f)                          */
#define TRIMSIR_RTC_X2TRIM_SHIFT            (21UL)                    /*!< X2TRIM (Bit 21)                                       */
#define TRIMSIR_RTC_X2TRIM_MASK             (0x3e00000UL)             /*!< X2TRIM (Bitfield-Mask: 0x1f)                          */
#define TRIMSIR_RTC_LOCK_SHIFT              (31UL)                    /*!< LOCK (Bit 31)                                         */
#define TRIMSIR_RTC_LOCK_MASK               (0x80000000UL)            /*!< LOCK (Bitfield-Mask: 0x01)                            */
/* =========================================================  SIMO  ========================================================== */
#define TRIMSIR_SIMO_CLKDIV_SHIFT           (0UL)                     /*!< CLKDIV (Bit 0)                                        */
#define TRIMSIR_SIMO_CLKDIV_MASK            (0x7UL)                   /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
/* =========================================================  IPOLO  ========================================================= */
#define TRIMSIR_IPOLO_IPO_LIMITLO_SHIFT     (0UL)                     /*!< IPO_LIMITLO (Bit 0)                                   */
#define TRIMSIR_IPOLO_IPO_LIMITLO_MASK      (0xffUL)                  /*!< IPO_LIMITLO (Bitfield-Mask: 0xff)                     */
/* =========================================================  CTRL  ========================================================== */
#define TRIMSIR_CTRL_VDDA_LIMITLO_SHIFT     (0UL)                     /*!< VDDA_LIMITLO (Bit 0)                                  */
#define TRIMSIR_CTRL_VDDA_LIMITLO_MASK      (0x7fUL)                  /*!< VDDA_LIMITLO (Bitfield-Mask: 0x7f)                    */
#define TRIMSIR_CTRL_VDDA_LIMITHI_SHIFT     (8UL)                     /*!< VDDA_LIMITHI (Bit 8)                                  */
#define TRIMSIR_CTRL_VDDA_LIMITHI_MASK      (0x7f00UL)                /*!< VDDA_LIMITHI (Bitfield-Mask: 0x7f)                    */
#define TRIMSIR_CTRL_IPO_LIMITHI_SHIFT      (15UL)                    /*!< IPO_LIMITHI (Bit 15)                                  */
#define TRIMSIR_CTRL_IPO_LIMITHI_MASK       (0xff8000UL)              /*!< IPO_LIMITHI (Bitfield-Mask: 0x1ff)                    */
#define TRIMSIR_CTRL_INRO_SEL_SHIFT         (24UL)                    /*!< INRO_SEL (Bit 24)                                     */
#define TRIMSIR_CTRL_INRO_SEL_MASK          (0x3000000UL)             /*!< INRO_SEL (Bitfield-Mask: 0x03)                        */
#define TRIMSIR_CTRL_INRO_TRIM_SHIFT        (29UL)                    /*!< INRO_TRIM (Bit 29)                                    */
#define TRIMSIR_CTRL_INRO_TRIM_MASK         (0xe0000000UL)            /*!< INRO_TRIM (Bitfield-Mask: 0x07)                       */
/* =========================================================  INRO  ========================================================== */
#define TRIMSIR_INRO_TRIM16K_SHIFT          (0UL)                     /*!< TRIM16K (Bit 0)                                       */
#define TRIMSIR_INRO_TRIM16K_MASK           (0x7UL)                   /*!< TRIM16K (Bitfield-Mask: 0x07)                         */
#define TRIMSIR_INRO_TRIM30K_SHIFT          (3UL)                     /*!< TRIM30K (Bit 3)                                       */
#define TRIMSIR_INRO_TRIM30K_MASK           (0x38UL)                  /*!< TRIM30K (Bitfield-Mask: 0x07)                         */
#define TRIMSIR_INRO_LPCLKSEL_SHIFT         (6UL)                     /*!< LPCLKSEL (Bit 6)                                      */
#define TRIMSIR_INRO_LPCLKSEL_MASK          (0xc0UL)                  /*!< LPCLKSEL (Bitfield-Mask: 0x03)                        */


/* =========================================================================================================================== */
/* ================                                            DVS                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  DVS_CTL  ======================================================== */
#define DVS_CTL_MON_ENA_SHIFT               (0UL)                     /*!< MON_ENA (Bit 0)                                       */
#define DVS_CTL_MON_ENA_MASK                (0x1UL)                   /*!< MON_ENA (Bitfield-Mask: 0x01)                         */
#define DVS_CTL_ADJ_ENA_SHIFT               (1UL)                     /*!< ADJ_ENA (Bit 1)                                       */
#define DVS_CTL_ADJ_ENA_MASK                (0x2UL)                   /*!< ADJ_ENA (Bitfield-Mask: 0x01)                         */
#define DVS_CTL_PS_FB_DIS_SHIFT             (2UL)                     /*!< PS_FB_DIS (Bit 2)                                     */
#define DVS_CTL_PS_FB_DIS_MASK              (0x4UL)                   /*!< PS_FB_DIS (Bitfield-Mask: 0x01)                       */
#define DVS_CTL_CTRL_TAP_ENA_SHIFT          (3UL)                     /*!< CTRL_TAP_ENA (Bit 3)                                  */
#define DVS_CTL_CTRL_TAP_ENA_MASK           (0x8UL)                   /*!< CTRL_TAP_ENA (Bitfield-Mask: 0x01)                    */
#define DVS_CTL_PROP_DLY_SHIFT              (4UL)                     /*!< PROP_DLY (Bit 4)                                      */
#define DVS_CTL_PROP_DLY_MASK               (0x30UL)                  /*!< PROP_DLY (Bitfield-Mask: 0x03)                        */
#define DVS_CTL_MON_ONESHOT_SHIFT           (6UL)                     /*!< MON_ONESHOT (Bit 6)                                   */
#define DVS_CTL_MON_ONESHOT_MASK            (0x40UL)                  /*!< MON_ONESHOT (Bitfield-Mask: 0x01)                     */
#define DVS_CTL_GO_DIRECT_SHIFT             (7UL)                     /*!< GO_DIRECT (Bit 7)                                     */
#define DVS_CTL_GO_DIRECT_MASK              (0x80UL)                  /*!< GO_DIRECT (Bitfield-Mask: 0x01)                       */
#define DVS_CTL_DIRECT_REG_SHIFT            (8UL)                     /*!< DIRECT_REG (Bit 8)                                    */
#define DVS_CTL_DIRECT_REG_MASK             (0x100UL)                 /*!< DIRECT_REG (Bitfield-Mask: 0x01)                      */
#define DVS_CTL_PRIME_ENA_SHIFT             (9UL)                     /*!< PRIME_ENA (Bit 9)                                     */
#define DVS_CTL_PRIME_ENA_MASK              (0x200UL)                 /*!< PRIME_ENA (Bitfield-Mask: 0x01)                       */
#define DVS_CTL_LIMIT_IE_SHIFT              (10UL)                    /*!< LIMIT_IE (Bit 10)                                     */
#define DVS_CTL_LIMIT_IE_MASK               (0x400UL)                 /*!< LIMIT_IE (Bitfield-Mask: 0x01)                        */
#define DVS_CTL_RANGE_IE_SHIFT              (11UL)                    /*!< RANGE_IE (Bit 11)                                     */
#define DVS_CTL_RANGE_IE_MASK               (0x800UL)                 /*!< RANGE_IE (Bitfield-Mask: 0x01)                        */
#define DVS_CTL_ADJ_IE_SHIFT                (12UL)                    /*!< ADJ_IE (Bit 12)                                       */
#define DVS_CTL_ADJ_IE_MASK                 (0x1000UL)                /*!< ADJ_IE (Bitfield-Mask: 0x01)                          */
#define DVS_CTL_REF_SEL_SHIFT               (13UL)                    /*!< REF_SEL (Bit 13)                                      */
#define DVS_CTL_REF_SEL_MASK                (0x1e000UL)               /*!< REF_SEL (Bitfield-Mask: 0x0f)                         */
#define DVS_CTL_INC_VAL_SHIFT               (17UL)                    /*!< INC_VAL (Bit 17)                                      */
#define DVS_CTL_INC_VAL_MASK                (0xe0000UL)               /*!< INC_VAL (Bitfield-Mask: 0x07)                         */
#define DVS_CTL_DVS_PS_APB_DIS_SHIFT        (20UL)                    /*!< DVS_PS_APB_DIS (Bit 20)                               */
#define DVS_CTL_DVS_PS_APB_DIS_MASK         (0x100000UL)              /*!< DVS_PS_APB_DIS (Bitfield-Mask: 0x01)                  */
#define DVS_CTL_DVS_HI_RANGE_ANY_SHIFT      (21UL)                    /*!< DVS_HI_RANGE_ANY (Bit 21)                             */
#define DVS_CTL_DVS_HI_RANGE_ANY_MASK       (0x200000UL)              /*!< DVS_HI_RANGE_ANY (Bitfield-Mask: 0x01)                */
#define DVS_CTL_FB_TO_IE_SHIFT              (22UL)                    /*!< FB_TO_IE (Bit 22)                                     */
#define DVS_CTL_FB_TO_IE_MASK               (0x400000UL)              /*!< FB_TO_IE (Bitfield-Mask: 0x01)                        */
#define DVS_CTL_FC_LV_IE_SHIFT              (23UL)                    /*!< FC_LV_IE (Bit 23)                                     */
#define DVS_CTL_FC_LV_IE_MASK               (0x800000UL)              /*!< FC_LV_IE (Bitfield-Mask: 0x01)                        */
#define DVS_CTL_PD_ACK_ENA_SHIFT            (24UL)                    /*!< PD_ACK_ENA (Bit 24)                                   */
#define DVS_CTL_PD_ACK_ENA_MASK             (0x1000000UL)             /*!< PD_ACK_ENA (Bitfield-Mask: 0x01)                      */
#define DVS_CTL_ADJ_ABORT_SHIFT             (25UL)                    /*!< ADJ_ABORT (Bit 25)                                    */
#define DVS_CTL_ADJ_ABORT_MASK              (0x2000000UL)             /*!< ADJ_ABORT (Bitfield-Mask: 0x01)                       */
/* =======================================================  DVS_STAT  ======================================================== */
#define DVS_STAT_DVS_STATE_SHIFT            (0UL)                     /*!< DVS_STATE (Bit 0)                                     */
#define DVS_STAT_DVS_STATE_MASK             (0xfUL)                   /*!< DVS_STATE (Bitfield-Mask: 0x0f)                       */
#define DVS_STAT_ADJ_UP_ENA_SHIFT           (4UL)                     /*!< ADJ_UP_ENA (Bit 4)                                    */
#define DVS_STAT_ADJ_UP_ENA_MASK            (0x10UL)                  /*!< ADJ_UP_ENA (Bitfield-Mask: 0x01)                      */
#define DVS_STAT_ADJ_DWN_ENA_SHIFT          (5UL)                     /*!< ADJ_DWN_ENA (Bit 5)                                   */
#define DVS_STAT_ADJ_DWN_ENA_MASK           (0x20UL)                  /*!< ADJ_DWN_ENA (Bitfield-Mask: 0x01)                     */
#define DVS_STAT_ADJ_ACTIVE_SHIFT           (6UL)                     /*!< ADJ_ACTIVE (Bit 6)                                    */
#define DVS_STAT_ADJ_ACTIVE_MASK            (0x40UL)                  /*!< ADJ_ACTIVE (Bitfield-Mask: 0x01)                      */
#define DVS_STAT_CTR_TAP_OK_SHIFT           (7UL)                     /*!< CTR_TAP_OK (Bit 7)                                    */
#define DVS_STAT_CTR_TAP_OK_MASK            (0x80UL)                  /*!< CTR_TAP_OK (Bitfield-Mask: 0x01)                      */
#define DVS_STAT_CTR_TAP_SEL_SHIFT          (8UL)                     /*!< CTR_TAP_SEL (Bit 8)                                   */
#define DVS_STAT_CTR_TAP_SEL_MASK           (0x100UL)                 /*!< CTR_TAP_SEL (Bitfield-Mask: 0x01)                     */
#define DVS_STAT_SLOW_TRIP_DET_SHIFT        (9UL)                     /*!< SLOW_TRIP_DET (Bit 9)                                 */
#define DVS_STAT_SLOW_TRIP_DET_MASK         (0x200UL)                 /*!< SLOW_TRIP_DET (Bitfield-Mask: 0x01)                   */
#define DVS_STAT_FAST_TRIP_DET_SHIFT        (10UL)                    /*!< FAST_TRIP_DET (Bit 10)                                */
#define DVS_STAT_FAST_TRIP_DET_MASK         (0x400UL)                 /*!< FAST_TRIP_DET (Bitfield-Mask: 0x01)                   */
#define DVS_STAT_PS_IN_RANGE_SHIFT          (11UL)                    /*!< PS_IN_RANGE (Bit 11)                                  */
#define DVS_STAT_PS_IN_RANGE_MASK           (0x800UL)                 /*!< PS_IN_RANGE (Bitfield-Mask: 0x01)                     */
#define DVS_STAT_PS_VCNTR_SHIFT             (12UL)                    /*!< PS_VCNTR (Bit 12)                                     */
#define DVS_STAT_PS_VCNTR_MASK              (0x7f000UL)               /*!< PS_VCNTR (Bitfield-Mask: 0x7f)                        */
#define DVS_STAT_MON_DLY_OK_SHIFT           (19UL)                    /*!< MON_DLY_OK (Bit 19)                                   */
#define DVS_STAT_MON_DLY_OK_MASK            (0x80000UL)               /*!< MON_DLY_OK (Bitfield-Mask: 0x01)                      */
#define DVS_STAT_ADJ_DLY_OK_SHIFT           (20UL)                    /*!< ADJ_DLY_OK (Bit 20)                                   */
#define DVS_STAT_ADJ_DLY_OK_MASK            (0x100000UL)              /*!< ADJ_DLY_OK (Bitfield-Mask: 0x01)                      */
#define DVS_STAT_LO_LIMIT_DET_SHIFT         (21UL)                    /*!< LO_LIMIT_DET (Bit 21)                                 */
#define DVS_STAT_LO_LIMIT_DET_MASK          (0x200000UL)              /*!< LO_LIMIT_DET (Bitfield-Mask: 0x01)                    */
#define DVS_STAT_HI_LIMIT_DET_SHIFT         (22UL)                    /*!< HI_LIMIT_DET (Bit 22)                                 */
#define DVS_STAT_HI_LIMIT_DET_MASK          (0x400000UL)              /*!< HI_LIMIT_DET (Bitfield-Mask: 0x01)                    */
#define DVS_STAT_VALID_TAP_SHIFT            (23UL)                    /*!< VALID_TAP (Bit 23)                                    */
#define DVS_STAT_VALID_TAP_MASK             (0x800000UL)              /*!< VALID_TAP (Bitfield-Mask: 0x01)                       */
#define DVS_STAT_LIMIT_ERR_SHIFT            (24UL)                    /*!< LIMIT_ERR (Bit 24)                                    */
#define DVS_STAT_LIMIT_ERR_MASK             (0x1000000UL)             /*!< LIMIT_ERR (Bitfield-Mask: 0x01)                       */
#define DVS_STAT_RANGE_ERR_SHIFT            (25UL)                    /*!< RANGE_ERR (Bit 25)                                    */
#define DVS_STAT_RANGE_ERR_MASK             (0x2000000UL)             /*!< RANGE_ERR (Bitfield-Mask: 0x01)                       */
#define DVS_STAT_ADJ_ERR_SHIFT              (26UL)                    /*!< ADJ_ERR (Bit 26)                                      */
#define DVS_STAT_ADJ_ERR_MASK               (0x4000000UL)             /*!< ADJ_ERR (Bitfield-Mask: 0x01)                         */
#define DVS_STAT_REF_SEL_ERR_SHIFT          (27UL)                    /*!< REF_SEL_ERR (Bit 27)                                  */
#define DVS_STAT_REF_SEL_ERR_MASK           (0x8000000UL)             /*!< REF_SEL_ERR (Bitfield-Mask: 0x01)                     */
#define DVS_STAT_FB_TO_ERR_SHIFT            (28UL)                    /*!< FB_TO_ERR (Bit 28)                                    */
#define DVS_STAT_FB_TO_ERR_MASK             (0x10000000UL)            /*!< FB_TO_ERR (Bitfield-Mask: 0x01)                       */
#define DVS_STAT_FB_TO_ERR_S_SHIFT          (29UL)                    /*!< FB_TO_ERR_S (Bit 29)                                  */
#define DVS_STAT_FB_TO_ERR_S_MASK           (0x20000000UL)            /*!< FB_TO_ERR_S (Bitfield-Mask: 0x01)                     */
#define DVS_STAT_FC_LV_DET_INT_SHIFT        (30UL)                    /*!< FC_LV_DET_INT (Bit 30)                                */
#define DVS_STAT_FC_LV_DET_INT_MASK         (0x40000000UL)            /*!< FC_LV_DET_INT (Bitfield-Mask: 0x01)                   */
#define DVS_STAT_FC_LV_DET_S_SHIFT          (31UL)                    /*!< FC_LV_DET_S (Bit 31)                                  */
#define DVS_STAT_FC_LV_DET_S_MASK           (0x80000000UL)            /*!< FC_LV_DET_S (Bitfield-Mask: 0x01)                     */
/* ======================================================  DVS_DIRECT  ======================================================= */
#define DVS_DIRECT_VOLTAGE_SHIFT            (0UL)                     /*!< VOLTAGE (Bit 0)                                       */
#define DVS_DIRECT_VOLTAGE_MASK             (0x7fUL)                  /*!< VOLTAGE (Bitfield-Mask: 0x7f)                         */
/* ========================================================  DVS_MON  ======================================================== */
#define DVS_MON_DLY_SHIFT                   (0UL)                     /*!< DLY (Bit 0)                                           */
#define DVS_MON_DLY_MASK                    (0xffffffUL)              /*!< DLY (Bitfield-Mask: 0xffffff)                         */
#define DVS_MON_PRE_SHIFT                   (24UL)                    /*!< PRE (Bit 24)                                          */
#define DVS_MON_PRE_MASK                    (0xff000000UL)            /*!< PRE (Bitfield-Mask: 0xff)                             */
/* ======================================================  DVS_ADJ_UP  ======================================================= */
#define DVS_ADJ_UP_DLY_SHIFT                (0UL)                     /*!< DLY (Bit 0)                                           */
#define DVS_ADJ_UP_DLY_MASK                 (0xffffUL)                /*!< DLY (Bitfield-Mask: 0xffff)                           */
#define DVS_ADJ_UP_PRE_SHIFT                (16UL)                    /*!< PRE (Bit 16)                                          */
#define DVS_ADJ_UP_PRE_MASK                 (0xff0000UL)              /*!< PRE (Bitfield-Mask: 0xff)                             */
/* ======================================================  DVS_ADJ_DWN  ====================================================== */
#define DVS_ADJ_DWN_DLY_SHIFT               (0UL)                     /*!< DLY (Bit 0)                                           */
#define DVS_ADJ_DWN_DLY_MASK                (0xffffUL)                /*!< DLY (Bitfield-Mask: 0xffff)                           */
#define DVS_ADJ_DWN_PRE_SHIFT               (16UL)                    /*!< PRE (Bit 16)                                          */
#define DVS_ADJ_DWN_PRE_MASK                (0xff0000UL)              /*!< PRE (Bitfield-Mask: 0xff)                             */
/* =====================================================  DVS_THRES_CMP  ===================================================== */
#define DVS_THRES_CMP_VCNTR_THRES_CNT_SHIFT (0UL)                     /*!< VCNTR_THRES_CNT (Bit 0)                               */
#define DVS_THRES_CMP_VCNTR_THRES_CNT_MASK  (0x7fUL)                  /*!< VCNTR_THRES_CNT (Bitfield-Mask: 0x7f)                 */
#define DVS_THRES_CMP_VCNTR_THRES_MASK_SHIFT (8UL)                    /*!< VCNTR_THRES_MASK (Bit 8)                              */
#define DVS_THRES_CMP_VCNTR_THRES_MASK_MASK  (0x7f00UL)               /*!< VCNTR_THRES_MASK (Bitfield-Mask: 0x7f)                */


/* =========================================================================================================================== */
/* ================                                         CAMERAIF                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  VER  ========================================================== */
#define CAMERAIF_VER_MINOR_SHIFT            (0UL)                     /*!< minor (Bit 0)                                         */
#define CAMERAIF_VER_MINOR_MASK             (0xffUL)                  /*!< minor (Bitfield-Mask: 0xff)                           */
#define CAMERAIF_VER_MAJOR_SHIFT            (8UL)                     /*!< major (Bit 8)                                         */
#define CAMERAIF_VER_MAJOR_MASK             (0xff00UL)                /*!< major (Bitfield-Mask: 0xff)                           */
/* =======================================================  FIFO_SIZE  ======================================================= */
#define CAMERAIF_FIFO_SIZE_FIFO_SIZE_SHIFT  (0UL)                     /*!< fifo_size (Bit 0)                                     */
#define CAMERAIF_FIFO_SIZE_FIFO_SIZE_MASK   (0xffUL)                  /*!< fifo_size (Bitfield-Mask: 0xff)                       */
/* =========================================================  CTRL  ========================================================== */
#define CAMERAIF_CTRL_READ_MODE_SHIFT       (0UL)                     /*!< READ_MODE (Bit 0)                                     */
#define CAMERAIF_CTRL_READ_MODE_MASK        (0x3UL)                   /*!< READ_MODE (Bitfield-Mask: 0x03)                       */
#define CAMERAIF_CTRL_DATA_WIDTH_SHIFT      (2UL)                     /*!< DATA_WIDTH (Bit 2)                                    */
#define CAMERAIF_CTRL_DATA_WIDTH_MASK       (0xcUL)                   /*!< DATA_WIDTH (Bitfield-Mask: 0x03)                      */
#define CAMERAIF_CTRL_DS_TIMING_EN_SHIFT    (4UL)                     /*!< DS_TIMING_EN (Bit 4)                                  */
#define CAMERAIF_CTRL_DS_TIMING_EN_MASK     (0x10UL)                  /*!< DS_TIMING_EN (Bitfield-Mask: 0x01)                    */
#define CAMERAIF_CTRL_FIFO_THRSH_SHIFT      (5UL)                     /*!< FIFO_THRSH (Bit 5)                                    */
#define CAMERAIF_CTRL_FIFO_THRSH_MASK       (0x3e0UL)                 /*!< FIFO_THRSH (Bitfield-Mask: 0x1f)                      */
#define CAMERAIF_CTRL_RX_DMA_SHIFT          (16UL)                    /*!< RX_DMA (Bit 16)                                       */
#define CAMERAIF_CTRL_RX_DMA_MASK           (0x10000UL)               /*!< RX_DMA (Bitfield-Mask: 0x01)                          */
#define CAMERAIF_CTRL_RX_DMA_THRSH_SHIFT    (17UL)                    /*!< RX_DMA_THRSH (Bit 17)                                 */
#define CAMERAIF_CTRL_RX_DMA_THRSH_MASK     (0x1e0000UL)              /*!< RX_DMA_THRSH (Bitfield-Mask: 0x0f)                    */
#define CAMERAIF_CTRL_THREE_CH_EN_SHIFT     (30UL)                    /*!< THREE_CH_EN (Bit 30)                                  */
#define CAMERAIF_CTRL_THREE_CH_EN_MASK      (0x40000000UL)            /*!< THREE_CH_EN (Bitfield-Mask: 0x01)                     */
#define CAMERAIF_CTRL_PCIF_SYS_SHIFT        (31UL)                    /*!< PCIF_SYS (Bit 31)                                     */
#define CAMERAIF_CTRL_PCIF_SYS_MASK         (0x80000000UL)            /*!< PCIF_SYS (Bitfield-Mask: 0x01)                        */
/* ========================================================  INT_EN  ========================================================= */
#define CAMERAIF_INT_EN_IMG_DONE_SHIFT      (0UL)                     /*!< IMG_DONE (Bit 0)                                      */
#define CAMERAIF_INT_EN_IMG_DONE_MASK       (0x1UL)                   /*!< IMG_DONE (Bitfield-Mask: 0x01)                        */
#define CAMERAIF_INT_EN_FIFO_FULL_SHIFT     (1UL)                     /*!< FIFO_FULL (Bit 1)                                     */
#define CAMERAIF_INT_EN_FIFO_FULL_MASK      (0x2UL)                   /*!< FIFO_FULL (Bitfield-Mask: 0x01)                       */
#define CAMERAIF_INT_EN_FIFO_THRESH_SHIFT   (2UL)                     /*!< FIFO_THRESH (Bit 2)                                   */
#define CAMERAIF_INT_EN_FIFO_THRESH_MASK    (0x4UL)                   /*!< FIFO_THRESH (Bitfield-Mask: 0x01)                     */
#define CAMERAIF_INT_EN_FIFO_NOT_EMPTY_SHIFT (3UL)                    /*!< FIFO_NOT_EMPTY (Bit 3)                                */
#define CAMERAIF_INT_EN_FIFO_NOT_EMPTY_MASK  (0x8UL)                  /*!< FIFO_NOT_EMPTY (Bitfield-Mask: 0x01)                  */
/* ========================================================  INT_FL  ========================================================= */
#define CAMERAIF_INT_FL_IMG_DONE_SHIFT      (0UL)                     /*!< IMG_DONE (Bit 0)                                      */
#define CAMERAIF_INT_FL_IMG_DONE_MASK       (0x1UL)                   /*!< IMG_DONE (Bitfield-Mask: 0x01)                        */
#define CAMERAIF_INT_FL_FIFO_FULL_SHIFT     (1UL)                     /*!< FIFO_FULL (Bit 1)                                     */
#define CAMERAIF_INT_FL_FIFO_FULL_MASK      (0x2UL)                   /*!< FIFO_FULL (Bitfield-Mask: 0x01)                       */
#define CAMERAIF_INT_FL_FIFO_THRESH_SHIFT   (2UL)                     /*!< FIFO_THRESH (Bit 2)                                   */
#define CAMERAIF_INT_FL_FIFO_THRESH_MASK    (0x4UL)                   /*!< FIFO_THRESH (Bitfield-Mask: 0x01)                     */
#define CAMERAIF_INT_FL_FIFO_NOT_EMPTY_SHIFT (3UL)                    /*!< FIFO_NOT_EMPTY (Bit 3)                                */
#define CAMERAIF_INT_FL_FIFO_NOT_EMPTY_MASK  (0x8UL)                  /*!< FIFO_NOT_EMPTY (Bitfield-Mask: 0x01)                  */
/* ====================================================  DS_TIMING_CODES  ==================================================== */
#define CAMERAIF_DS_TIMING_CODES_SAV_SHIFT  (0UL)                     /*!< SAV (Bit 0)                                           */
#define CAMERAIF_DS_TIMING_CODES_SAV_MASK   (0xffUL)                  /*!< SAV (Bitfield-Mask: 0xff)                             */
#define CAMERAIF_DS_TIMING_CODES_EAV_SHIFT  (8UL)                     /*!< EAV (Bit 8)                                           */
#define CAMERAIF_DS_TIMING_CODES_EAV_MASK   (0xff00UL)                /*!< EAV (Bitfield-Mask: 0xff)                             */
/* =======================================================  FIFO_DATA  ======================================================= */
#define CAMERAIF_FIFO_DATA_DATA_SHIFT       (0UL)                     /*!< DATA (Bit 0)                                          */
#define CAMERAIF_FIFO_DATA_DATA_MASK        (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                            WUT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
/* ==========================================================  CMP  ========================================================== */
/* ==========================================================  PWM  ========================================================== */
/* =========================================================  INTR  ========================================================== */
#define WUT_INTR_IRQ_CLR_SHIFT              (0UL)                     /*!< IRQ_CLR (Bit 0)                                       */
#define WUT_INTR_IRQ_CLR_MASK               (0x1UL)                   /*!< IRQ_CLR (Bitfield-Mask: 0x01)                         */
/* =========================================================  CTRL  ========================================================== */
#define WUT_CTRL_TMODE_SHIFT                (0UL)                     /*!< TMODE (Bit 0)                                         */
#define WUT_CTRL_TMODE_MASK                 (0x7UL)                   /*!< TMODE (Bitfield-Mask: 0x07)                           */
#define WUT_CTRL_PRES_SHIFT                 (3UL)                     /*!< PRES (Bit 3)                                          */
#define WUT_CTRL_PRES_MASK                  (0x38UL)                  /*!< PRES (Bitfield-Mask: 0x07)                            */
#define WUT_CTRL_TPOL_SHIFT                 (6UL)                     /*!< TPOL (Bit 6)                                          */
#define WUT_CTRL_TPOL_MASK                  (0x40UL)                  /*!< TPOL (Bitfield-Mask: 0x01)                            */
#define WUT_CTRL_TEN_SHIFT                  (7UL)                     /*!< TEN (Bit 7)                                           */
#define WUT_CTRL_TEN_MASK                   (0x80UL)                  /*!< TEN (Bitfield-Mask: 0x01)                             */
#define WUT_CTRL_PRES3_SHIFT                (8UL)                     /*!< PRES3 (Bit 8)                                         */
#define WUT_CTRL_PRES3_MASK                 (0x100UL)                 /*!< PRES3 (Bitfield-Mask: 0x01)                           */
#define WUT_CTRL_PWMSYNC_SHIFT              (9UL)                     /*!< PWMSYNC (Bit 9)                                       */
#define WUT_CTRL_PWMSYNC_MASK               (0x200UL)                 /*!< PWMSYNC (Bitfield-Mask: 0x01)                         */
#define WUT_CTRL_NOLHPOL_SHIFT              (10UL)                    /*!< NOLHPOL (Bit 10)                                      */
#define WUT_CTRL_NOLHPOL_MASK               (0x400UL)                 /*!< NOLHPOL (Bitfield-Mask: 0x01)                         */
#define WUT_CTRL_NOLLPOL_SHIFT              (11UL)                    /*!< NOLLPOL (Bit 11)                                      */
#define WUT_CTRL_NOLLPOL_MASK               (0x800UL)                 /*!< NOLLPOL (Bitfield-Mask: 0x01)                         */
#define WUT_CTRL_PWMCKBD_SHIFT              (12UL)                    /*!< PWMCKBD (Bit 12)                                      */
#define WUT_CTRL_PWMCKBD_MASK               (0x1000UL)                /*!< PWMCKBD (Bitfield-Mask: 0x01)                         */
/* ========================================================  NOLCMP  ========================================================= */
#define WUT_NOLCMP_NOLLCMP_SHIFT            (0UL)                     /*!< NOLLCMP (Bit 0)                                       */
#define WUT_NOLCMP_NOLLCMP_MASK             (0xffUL)                  /*!< NOLLCMP (Bitfield-Mask: 0xff)                         */
#define WUT_NOLCMP_NOLHCMP_SHIFT            (8UL)                     /*!< NOLHCMP (Bit 8)                                       */
#define WUT_NOLCMP_NOLHCMP_MASK             (0xff00UL)                /*!< NOLHCMP (Bitfield-Mask: 0xff)                         */
/* ========================================================  PRESET  ========================================================= */
/* ========================================================  RELOAD  ========================================================= */
/* =======================================================  SNAPSHOT  ======================================================== */

/** @} */ /* End of group PosMask_peripherals */

/******************************************************************************/
/*                                                                  SCB CPACR */

/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
#define SCB_CPACR_CP10_Pos              20                              /*!< SCB CPACR: Coprocessor 10 Position */
#define SCB_CPACR_CP10_Msk              (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
#define SCB_CPACR_CP11_Pos              22                              /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk              (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */

#ifdef __cplusplus
}
#endif

#endif /* MAX78000_H */


/** @} */ /* End of group MAX78000 */

/** @} */ /* End of group Maxim-Integrated */
